From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:58530) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCxgx-0002oP-Jp for qemu-devel@nongnu.org; Fri, 23 Aug 2013 16:10:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VCxgr-0005vh-2S for qemu-devel@nongnu.org; Fri, 23 Aug 2013 16:10:43 -0400 Received: from mail-pd0-f178.google.com ([209.85.192.178]:47706) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VCxgq-0005vV-Ms for qemu-devel@nongnu.org; Fri, 23 Aug 2013 16:10:36 -0400 Received: by mail-pd0-f178.google.com with SMTP id w10so1086331pde.37 for ; Fri, 23 Aug 2013 13:10:36 -0700 (PDT) From: Christoffer Dall Date: Fri, 23 Aug 2013 13:10:21 -0700 Message-Id: <1377288624-7418-3-git-send-email-christoffer.dall@linaro.org> In-Reply-To: <1377288624-7418-1-git-send-email-christoffer.dall@linaro.org> References: <1377288624-7418-1-git-send-email-christoffer.dall@linaro.org> Subject: [Qemu-devel] [PATCH 2/5] hw: arm_gic: Introduce GIC_SET_PRIORITY macro List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: linaro-kernel@lists.linaro.org, kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this macro to set the priority of interrupts. Signed-off-by: Christoffer Dall --- hw/intc/arm_gic.c | 6 +----- hw/intc/gic_internal.h | 6 ++++++ 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index bff3f9e..a7bb528 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -444,11 +444,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x400) + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < GIC_INTERNAL) { - s->priority1[irq][cpu] = value; - } else { - s->priority2[irq - GIC_INTERNAL] = value; - } + GIC_SET_PRIORITY(irq, cpu, value); } else if (offset < 0xc00) { /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the * annoying exception of the 11MPCore's GIC. diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 1426437..d835aa1 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -57,6 +57,12 @@ #define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \ s->priority1[irq][cpu] : \ s->priority2[(irq) - GIC_INTERNAL]) +#define GIC_SET_PRIORITY(irq, cpu, val) do { \ + uint8_t *__x = ((irq) < GIC_INTERNAL) ? \ + &s->priority1[irq][cpu] : \ + &s->priority2[(irq) - GIC_INTERNAL]; \ + *__x = val; \ +} while (0) #define GIC_TARGET(irq) s->irq_target[irq] typedef struct gic_irq_state { -- 1.7.10.4