From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52441) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VD4s3-0007LA-R9 for qemu-devel@nongnu.org; Fri, 23 Aug 2013 23:50:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VD4rv-0002Xw-69 for qemu-devel@nongnu.org; Fri, 23 Aug 2013 23:50:39 -0400 Received: from mail-ea0-x235.google.com ([2a00:1450:4013:c01::235]:34361) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VD4ru-0002Xj-Ht for qemu-devel@nongnu.org; Fri, 23 Aug 2013 23:50:30 -0400 Received: by mail-ea0-f181.google.com with SMTP id d10so611938eaj.12 for ; Fri, 23 Aug 2013 20:50:29 -0700 (PDT) Sender: Paolo Bonzini From: Paolo Bonzini Date: Sat, 24 Aug 2013 05:50:01 +0200 Message-Id: <1377316202-2849-9-git-send-email-pbonzini@redhat.com> In-Reply-To: <1377316202-2849-1-git-send-email-pbonzini@redhat.com> References: <1377316202-2849-1-git-send-email-pbonzini@redhat.com> Subject: [Qemu-devel] [PULL 8/9] kvm: i386: fix LAPIC TSC deadline timer save/restore List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Marcelo Tosatti , anthony@codemonkey.ws, gleb@redhat.com From: Marcelo Tosatti The configuration of the timer represented by MSR_IA32_TSCDEADLINE depends on: - APIC LVT Timer register. - TSC value. Change the order to respect the dependency. Signed-off-by: Marcelo Tosatti Signed-off-by: Paolo Bonzini --- target-i386/kvm.c | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 7bb8455..58f7bb7 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1073,6 +1073,26 @@ static void kvm_msr_entry_set(struct kvm_msr_entry *entry, entry->data = value; } +static int kvm_put_tscdeadline_msr(X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + struct { + struct kvm_msrs info; + struct kvm_msr_entry entries[1]; + } msr_data; + struct kvm_msr_entry *msrs = msr_data.entries; + + if (!has_msr_tsc_deadline) { + return 0; + } + + kvm_msr_entry_set(&msrs[0], MSR_IA32_TSCDEADLINE, env->tsc_deadline); + + msr_data.info.nmsrs = 1; + + return kvm_vcpu_ioctl(CPU(cpu), KVM_SET_MSRS, &msr_data); +} + static int kvm_put_msrs(X86CPU *cpu, int level) { CPUX86State *env = &cpu->env; @@ -1096,9 +1116,6 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_tsc_adjust) { kvm_msr_entry_set(&msrs[n++], MSR_TSC_ADJUST, env->tsc_adjust); } - if (has_msr_tsc_deadline) { - kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSCDEADLINE, env->tsc_deadline); - } if (has_msr_misc_enable) { kvm_msr_entry_set(&msrs[n++], MSR_IA32_MISC_ENABLE, env->msr_ia32_misc_enable); @@ -1808,6 +1825,12 @@ int kvm_arch_put_registers(CPUState *cpu, int level) return ret; } } + + ret = kvm_put_tscdeadline_msr(x86_cpu); + if (ret < 0) { + return ret; + } + ret = kvm_put_vcpu_events(x86_cpu, level); if (ret < 0) { return ret; -- 1.8.3.1