From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38436) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VEENA-00078O-0W for qemu-devel@nongnu.org; Tue, 27 Aug 2013 04:11:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VEEN2-0000rA-M3 for qemu-devel@nongnu.org; Tue, 27 Aug 2013 04:11:31 -0400 Received: from mail-pd0-f180.google.com ([209.85.192.180]:56528) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VEEN2-0000qz-F3 for qemu-devel@nongnu.org; Tue, 27 Aug 2013 04:11:24 -0400 Received: by mail-pd0-f180.google.com with SMTP id y10so4498663pdj.39 for ; Tue, 27 Aug 2013 01:11:07 -0700 (PDT) From: Liu Ping Fan Date: Tue, 27 Aug 2013 16:10:44 +0800 Message-Id: <1377591046-1944-1-git-send-email-pingfank@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v2 1/3] hpet: inverse polarity when pin above ISA_NUM_IRQS List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Anthony Liguori , Jan Kiszka According to hpet spec, hpet irq is high active. But according to ICH spec, there is inversion before the input of ioapic. So the OS will expect low active on this IRQ line.(And this is observed on bare metal). We fold the emulation of this inversion inside the hpet logic. Signed-off-by: Liu Ping Fan --- hw/timer/hpet.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 648b383..1139448 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -198,13 +198,23 @@ static void update_irq(struct HPETTimer *timer, int set) if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) { s->isr &= ~mask; if (!timer_fsb_route(timer)) { - qemu_irq_lower(s->irqs[route]); + /* fold the ICH PIRQ# pin's internal inversion logic into hpet */ + if (route >= ISA_NUM_IRQS) { + qemu_irq_raise(s->irqs[route]); + } else { + qemu_irq_lower(s->irqs[route]); + } } } else if (timer_fsb_route(timer)) { stl_le_phys(timer->fsb >> 32, timer->fsb & 0xffffffff); } else if (timer->config & HPET_TN_TYPE_LEVEL) { s->isr |= mask; - qemu_irq_raise(s->irqs[route]); + /* fold the ICH PIRQ# pin's internal inversion logic into hpet */ + if (route >= ISA_NUM_IRQS) { + qemu_irq_lower(s->irqs[route]); + } else { + qemu_irq_raise(s->irqs[route]); + } } else { s->isr &= ~mask; qemu_irq_pulse(s->irqs[route]); -- 1.8.1.4