From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39471) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VEGa2-00086X-CW for qemu-devel@nongnu.org; Tue, 27 Aug 2013 06:33:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VEGZw-0002Bf-Dh for qemu-devel@nongnu.org; Tue, 27 Aug 2013 06:32:58 -0400 Message-ID: <1377599548.3819.133.camel@pasglop> From: Benjamin Herrenschmidt Date: Tue, 27 Aug 2013 20:32:28 +1000 In-Reply-To: <20130827102647.GA24655@redhat.com> References: <1375865493-19143-1-git-send-email-aik@ozlabs.ru> <1375865493-19143-2-git-send-email-aik@ozlabs.ru> <20130819073550.GE17937@redhat.com> <5211CCC4.3010606@ozlabs.ru> <20130819075434.GA18579@redhat.com> <5211D2D9.5050101@ozlabs.ru> <20130819090128.GA20139@redhat.com> <5216E530.4060007@ozlabs.ru> <6CCA8220-0125-4CB5-A54E-9648D8B409D2@suse.de> <20130827102647.GA24655@redhat.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 1/2] kvm irqfd: support msimessage to irq translation in PHB List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: Anthony Liguori , Alexey Kardashevskiy , Alexander Graf , qemu-devel@nongnu.org, Alex Williamson , qemu-ppc@nongnu.org, Paolo Bonzini , Paul Mackerras On Tue, 2013-08-27 at 13:26 +0300, Michael S. Tsirkin wrote: > e would end up with something like > > > > diff --git a/kvm-all.c b/kvm-all.c > > index 716860f..ca3251e 100644 > > --- a/kvm-all.c > > +++ b/kvm-all.c > > @@ -1190,6 +1190,10 @@ int kvm_irqchip_add_msi_route(KVMState *s, MSIMessage msg) > > struct kvm_irq_routing_entry kroute = {}; > > int virq; > > > > + if (kvm_gsi_routing_linear()) { > > + return msi.data & 0xffff; > > + } > > + I haven't followed the whole discussion, Alexey, is this the per-host bridge source number or the global XIRR (XICS interrupt number) ? Because in the latter case, it can be up to 24 bits... (And yes, MSI data is limited to 16). However maybe we can decide arbitrarily that under qemu/kvm we only support 16-bit XIRRs (it's fine, from a PAPR perspective at least if it keep things simpler). Cheers, Ben.