From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38786) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VF9Bz-0002cE-5N for qemu-devel@nongnu.org; Thu, 29 Aug 2013 16:51:47 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VF9Bq-0004AH-H2 for qemu-devel@nongnu.org; Thu, 29 Aug 2013 16:51:47 -0400 Received: from hall.aurel32.net ([2001:470:1f0b:4a8::1]:40403) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VF9Bq-00049y-9f for qemu-devel@nongnu.org; Thu, 29 Aug 2013 16:51:38 -0400 From: Aurelien Jarno Date: Thu, 29 Aug 2013 22:51:24 +0200 Message-Id: <1377809485-24004-3-git-send-email-aurelien@aurel32.net> In-Reply-To: <1377809485-24004-1-git-send-email-aurelien@aurel32.net> References: <1377809485-24004-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH v3 2/3] tcg/mips: inline bswap16/bswap32 ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Aurelien Jarno Use an inline version for the bswap16 and bswap32 ops to avoid testing for MIPS32R2 instructions availability, as these ops are only available in that case. Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 9b518c2..daaf722 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1506,13 +1506,12 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; - /* The bswap routines do not work on non-R2 CPU. In that case - we let TCG generating the corresponding code. */ case INDEX_op_bswap16_i32: - tcg_out_bswap16(s, args[0], args[1]); + tcg_out_opc_reg(s, OPC_WSBH, args[0], 0, args[1]); break; case INDEX_op_bswap32_i32: - tcg_out_bswap32(s, args[0], args[1]); + tcg_out_opc_reg(s, OPC_WSBH, args[0], 0, args[1]); + tcg_out_opc_sa(s, OPC_ROTR, args[0], args[0], 16); break; case INDEX_op_ext8s_i32: -- 1.7.10.4