From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42451) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VF9UM-0003WY-4L for qemu-devel@nongnu.org; Thu, 29 Aug 2013 17:10:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VF9UB-0001qo-9P for qemu-devel@nongnu.org; Thu, 29 Aug 2013 17:10:45 -0400 Received: from e06smtp16.uk.ibm.com ([195.75.94.112]:60559) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VF9UA-0001qC-Fz for qemu-devel@nongnu.org; Thu, 29 Aug 2013 17:10:34 -0400 Received: from /spool/local by e06smtp16.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Thu, 29 Aug 2013 22:03:42 +0100 Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by d06dlp01.portsmouth.uk.ibm.com (Postfix) with ESMTP id 54EDE17D805A for ; Thu, 29 Aug 2013 22:10:30 +0100 (BST) Received: from d06av05.portsmouth.uk.ibm.com (d06av05.portsmouth.uk.ibm.com [9.149.37.229]) by b06cxnps4075.portsmouth.uk.ibm.com (8.13.8/8.13.8/NCO v10.0) with ESMTP id r7TLAI0Y459136 for ; Thu, 29 Aug 2013 21:10:18 GMT Received: from d06av05.portsmouth.uk.ibm.com (localhost [127.0.0.1]) by d06av05.portsmouth.uk.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id r7TLATx8025433 for ; Thu, 29 Aug 2013 15:10:29 -0600 From: Christian Borntraeger Date: Thu, 29 Aug 2013 23:10:47 +0200 Message-Id: <1377810649-47484-5-git-send-email-borntraeger@de.ibm.com> In-Reply-To: <1377810649-47484-1-git-send-email-borntraeger@de.ibm.com> References: <1377810649-47484-1-git-send-email-borntraeger@de.ibm.com> Subject: [Qemu-devel] [PULL 4/6] s390/cpu: split CPU reset into architectured functions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Cornelia Huck , Christian Borntraeger , Jens Freimann , =?UTF-8?q?Andreas=20F=C3=A4rber?= , qemu-devel s390 provides several CPU resets: - CPU reset, clears interrupts, stop processing, clears TLB, but does not touch registers - initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC, timer and control registers. It does not touch gprs, fprs and acrs (!) - Power on reset: the full monty wire up CPUClass reset to the full monty, but provide the lesser resets as part of S390CPUClass. Signed-off-by: Christian Borntraeger --- target-s390x/cpu-qom.h | 4 ++++ target-s390x/cpu.c | 41 +++++++++++++++++++++++++++++++++-------- 2 files changed, 37 insertions(+), 8 deletions(-) diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h index 2dc1750..ac0460e 100644 --- a/target-s390x/cpu-qom.h +++ b/target-s390x/cpu-qom.h @@ -37,6 +37,8 @@ * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * @load_normal: Performs a load normal. + * @cpu_reset: Performs a CPU reset. + * @initial_cpu_reset: Performs an initial CPU reset. * * An S/390 CPU model. */ @@ -48,6 +50,8 @@ typedef struct S390CPUClass { DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); void (*load_normal)(CPUState *cpu); + void (*cpu_reset)(CPUState *cpu); + void (*initial_cpu_reset)(CPUState *cpu); } S390CPUClass; /** diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 69f5e10..b0af043 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -76,7 +76,7 @@ static void s390_cpu_load_normal(CPUState *s) } #endif -/* CPUClass::reset() */ +/* S390CPUClass::cpu_reset() */ static void s390_cpu_reset(CPUState *s) { S390CPU *cpu = S390_CPU(s); @@ -87,11 +87,6 @@ static void s390_cpu_reset(CPUState *s) scc->parent_reset(s); - memset(env, 0, offsetof(CPUS390XState, breakpoints)); - - /* architectured initial values for CR 0 and 14 */ - env->cregs[0] = CR0_RESET; - env->cregs[14] = CR14_RESET; /* set halted to 1 to make sure we can add the cpu in * s390_ipl_cpu code, where CPUState::halted is set back to 0 * after incrementing the cpu counter */ @@ -110,6 +105,35 @@ static void s390_cpu_machine_reset_cb(void *opaque) } #endif +/* S390CPUClass::initial_reset() */ +static void s390_cpu_initial_reset(CPUState *s) +{ + S390CPU *cpu = S390_CPU(s); + CPUS390XState *env = &cpu->env; + + s390_cpu_reset(s); + /* initial reset does not touch regs,fregs and aregs */ + memset(&env->fpc, 0, offsetof(CPUS390XState, breakpoints) - + offsetof(CPUS390XState, fpc)); + + /* architectured initial values for CR 0 and 14 */ + env->cregs[0] = CR0_RESET; + env->cregs[14] = CR14_RESET; +} + +/* CPUClass:reset() */ +static void s390_cpu_full_reset(CPUState *s) +{ + S390CPU *cpu = S390_CPU(s); + CPUS390XState *env = &cpu->env; + + s390_cpu_initial_reset(s); + /* also reset regs,aregs and fregs */ + memset(env, 0, offsetof(CPUS390XState, fpc)); +} + + + static void s390_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs = CPU(dev); @@ -183,8 +207,9 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) #if !defined(CONFIG_USER_ONLY) scc->load_normal = s390_cpu_load_normal; #endif - cc->reset = s390_cpu_reset; - + scc->cpu_reset = s390_cpu_reset; + scc->initial_cpu_reset = s390_cpu_initial_reset; + cc->reset = s390_cpu_full_reset; cc->do_interrupt = s390_cpu_do_interrupt; cc->dump_state = s390_cpu_dump_state; cc->set_pc = s390_cpu_set_pc; -- 1.8.3.1