From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40912) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VFSnR-0005Ul-KI for qemu-devel@nongnu.org; Fri, 30 Aug 2013 13:47:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VFSnL-0007Gg-LF for qemu-devel@nongnu.org; Fri, 30 Aug 2013 13:47:45 -0400 Received: from mail-pb0-x22f.google.com ([2607:f8b0:400e:c01::22f]:59060) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VFSnL-0007GW-9i for qemu-devel@nongnu.org; Fri, 30 Aug 2013 13:47:39 -0400 Received: by mail-pb0-f47.google.com with SMTP id rr4so2142209pbb.20 for ; Fri, 30 Aug 2013 10:47:38 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Fri, 30 Aug 2013 10:47:16 -0700 Message-Id: <1377884837-6581-8-git-send-email-rth@twiddle.net> In-Reply-To: <1377884837-6581-1-git-send-email-rth@twiddle.net> References: <1377884837-6581-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v2 7/8] tcg-arm: Remove restriction on qemu_ld output register List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net The main intent of the patch is to allow the tlb addend register to be changed, without tying that change to the constraint. But the most common side-effect seems to be to enable usage of ldrd with the r0,r1 pair. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 49 +++++++++++++++++++++++++++++-------------------- 1 file changed, 29 insertions(+), 20 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index d27c365..ff331a1 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -183,15 +183,6 @@ static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str) tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); #endif break; - case 'L': - ct->ct |= TCG_CT_REG; - tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1); -#ifdef CONFIG_SOFTMMU - /* r1 is still needed to load data_reg or data_reg2, - so don't use it. */ - tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); -#endif - break; /* qemu_st address & data_reg */ case 's': @@ -1313,8 +1304,17 @@ static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0); break; case 3: - tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0); - tcg_out_mov_reg(s, COND_AL, data_reg2, TCG_REG_R1); + if (data_reg != TCG_REG_R1) { + tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0); + tcg_out_mov_reg(s, COND_AL, data_reg2, TCG_REG_R1); + } else if (data_reg2 != TCG_REG_R0) { + tcg_out_mov_reg(s, COND_AL, data_reg2, TCG_REG_R1); + tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_R0); + } else { + tcg_out_mov_reg(s, COND_AL, TCG_REG_TMP, TCG_REG_R0); + tcg_out_mov_reg(s, COND_AL, data_reg2, TCG_REG_R1); + tcg_out_mov_reg(s, COND_AL, data_reg, TCG_REG_TMP); + } break; } @@ -1420,16 +1420,25 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) break; case 3: if (bswap) { - tcg_out_ld32_rwb(s, COND_AL, data_reg2, addend, addr_reg); - tcg_out_ld32_12(s, COND_AL, data_reg, addend, 4); - tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2); - tcg_out_bswap32(s, COND_AL, data_reg, data_reg); - } else if (use_armv6_instructions - && (data_reg & 1) == 0 && data_reg2 == data_reg + 1) { + TCGReg t = data_reg; + data_reg = data_reg2; + data_reg2 = t; + } + if (use_armv6_instructions + && (data_reg & 1) == 0 && data_reg2 == data_reg + 1) { tcg_out_ldrd_r(s, COND_AL, data_reg, addr_reg, addend); - } else { + } else if (data_reg != addend) { tcg_out_ld32_rwb(s, COND_AL, data_reg, addend, addr_reg); tcg_out_ld32_12(s, COND_AL, data_reg2, addend, 4); + } else { + tcg_out_dat_reg(s, COND_AL, ARITH_ADD, TCG_REG_TMP, + addend, addr_reg, SHIFT_IMM_LSL(0)); + tcg_out_ld32_12(s, COND_AL, data_reg, TCG_REG_TMP, 0); + tcg_out_ld32_12(s, COND_AL, data_reg2, TCG_REG_TMP, 4); + } + if (bswap) { + tcg_out_bswap32(s, COND_AL, data_reg2, data_reg2); + tcg_out_bswap32(s, COND_AL, data_reg, data_reg); } break; } @@ -2024,7 +2033,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "l" } }, { INDEX_op_qemu_ld16s, { "r", "l" } }, { INDEX_op_qemu_ld32, { "r", "l" } }, - { INDEX_op_qemu_ld64, { "L", "L", "l" } }, + { INDEX_op_qemu_ld64, { "r", "r", "l" } }, { INDEX_op_qemu_st8, { "s", "s" } }, { INDEX_op_qemu_st16, { "s", "s" } }, @@ -2036,7 +2045,7 @@ static const TCGTargetOpDef arm_op_defs[] = { { INDEX_op_qemu_ld16u, { "r", "l", "l" } }, { INDEX_op_qemu_ld16s, { "r", "l", "l" } }, { INDEX_op_qemu_ld32, { "r", "l", "l" } }, - { INDEX_op_qemu_ld64, { "L", "L", "l", "l" } }, + { INDEX_op_qemu_ld64, { "r", "r", "l", "l" } }, { INDEX_op_qemu_st8, { "s", "s", "s" } }, { INDEX_op_qemu_st16, { "s", "s", "s" } }, -- 1.8.1.4