From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38589) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGVTL-0000WL-4P for qemu-devel@nongnu.org; Mon, 02 Sep 2013 10:51:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGVTD-0005am-Rj for qemu-devel@nongnu.org; Mon, 02 Sep 2013 10:51:19 -0400 Received: from mx1.redhat.com ([209.132.183.28]:13205) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGVTD-0005aP-GB for qemu-devel@nongnu.org; Mon, 02 Sep 2013 10:51:11 -0400 Message-ID: <1378133472.2640.26.camel@localhost.localdomain> From: Marcel Apfelbaum Date: Mon, 02 Sep 2013 17:51:12 +0300 In-Reply-To: <20130902144836.GA27783@redhat.com> References: <1378131189-25538-1-git-send-email-marcel.a@redhat.com> <1378131189-25538-3-git-send-email-marcel.a@redhat.com> <20130902144836.GA27783@redhat.com> Content-Type: text/plain; charset="UTF-8" Mime-Version: 1.0 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH RFC 2/3] hw/pci: add MemoryRegion ops for unassigned pci addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: pbonzini@redhat.com, aliguori@us.ibm.com, qemu-devel@nongnu.org, afaerber@suse.de On Mon, 2013-09-02 at 17:48 +0300, Michael S. Tsirkin wrote: > On Mon, Sep 02, 2013 at 05:13:08PM +0300, Marcel Apfelbaum wrote: > > The MemoryRegions assigned with this ops shall "intercept" > > the accesses to unassigned pci address space and the > > associated callback will set MASTER ABORT bit in the > > STATUS register of the device that initiated the > > transaction as defined in PCI spec. > > > > Note: This implementation assumes that all the reads/writes to > > the pci address space are done by the cpu. > > > > Signed-off-by: Marcel Apfelbaum > > --- > > hw/pci/pci.c | 18 ++++++++++++++++++ > > include/hw/pci/pci.h | 3 +++ > > 2 files changed, 21 insertions(+) > > > > diff --git a/hw/pci/pci.c b/hw/pci/pci.c > > index 4c004f5..f0289fc 100644 > > --- a/hw/pci/pci.c > > +++ b/hw/pci/pci.c > > @@ -2229,6 +2229,24 @@ MemoryRegion *pci_address_space_io(PCIDevice *dev) > > return dev->bus->address_space_io; > > } > > > > +static bool pci_unassigned_mem_accepts(void *opaque, hwaddr addr, > > + unsigned size, bool is_write) > > +{ > > + PCIDevice *d = opaque; > > + > > + /* FIXME assumption: the cpu initiated the pci transaction > > + * and not another pci device */ > > /* > * Multiline > * comments > */ Got it. Thanks! Marcel > > > > + pci_word_test_and_set_mask(d->config + PCI_STATUS, > > + PCI_STATUS_REC_MASTER_ABORT); > > + > > + return false; > > +} > > + > > +const MemoryRegionOps pci_unassigned_mem_ops = { > > + .valid.accepts = pci_unassigned_mem_accepts, > > + .endianness = DEVICE_NATIVE_ENDIAN, > > +}; > > + > > static void pci_device_class_init(ObjectClass *klass, void *data) > > { > > DeviceClass *k = DEVICE_CLASS(klass); > > diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h > > index ccec2ba..854681c 100644 > > --- a/include/hw/pci/pci.h > > +++ b/include/hw/pci/pci.h > > @@ -329,6 +329,9 @@ int pci_device_load(PCIDevice *s, QEMUFile *f); > > MemoryRegion *pci_address_space(PCIDevice *dev); > > MemoryRegion *pci_address_space_io(PCIDevice *dev); > > > > +#define PCI_UNASSIGNED_MEM_PRIORITY -1 > > +extern const MemoryRegionOps pci_unassigned_mem_ops; > > + > > typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level); > > typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); > > typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin); > > -- > > 1.8.3.1 >