From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:39737) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGX0K-0002Js-3p for qemu-devel@nongnu.org; Mon, 02 Sep 2013 12:29:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGX0F-0005gF-2L for qemu-devel@nongnu.org; Mon, 02 Sep 2013 12:29:28 -0400 Received: from mail-pd0-x233.google.com ([2607:f8b0:400e:c02::233]:35091) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGX0E-0005g5-RB for qemu-devel@nongnu.org; Mon, 02 Sep 2013 12:29:22 -0400 Received: by mail-pd0-f179.google.com with SMTP id v10so4909105pde.24 for ; Mon, 02 Sep 2013 09:29:22 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 2 Sep 2013 09:28:47 -0700 Message-Id: <1378139354-28602-3-git-send-email-rth@twiddle.net> In-Reply-To: <1378139354-28602-1-git-send-email-rth@twiddle.net> References: <1378139354-28602-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 02/29] tcg-mips: Implement mulsh, muluh List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net, anthony@codemonkey.ws With the optimization in tcg_liveness_analysis, we can avoid the MFLO when it is unused. Reviewed-by: Aurelien Jarno Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c | 10 ++++++++++ tcg/mips/tcg-target.h | 4 ++-- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index 793532e..31cd514 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -1423,6 +1423,14 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); tcg_out_opc_reg(s, OPC_MFHI, args[1], 0, 0); break; + case INDEX_op_mulsh_i32: + tcg_out_opc_reg(s, OPC_MULT, 0, args[1], args[2]); + tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0); + break; + case INDEX_op_muluh_i32: + tcg_out_opc_reg(s, OPC_MULTU, 0, args[1], args[2]); + tcg_out_opc_reg(s, OPC_MFHI, args[0], 0, 0); + break; case INDEX_op_div_i32: tcg_out_opc_reg(s, OPC_DIV, 0, args[1], args[2]); tcg_out_opc_reg(s, OPC_MFLO, args[0], 0, 0); @@ -1602,6 +1610,8 @@ static const TCGTargetOpDef mips_op_defs[] = { { INDEX_op_mul_i32, { "r", "rZ", "rZ" } }, { INDEX_op_muls2_i32, { "r", "r", "rZ", "rZ" } }, { INDEX_op_mulu2_i32, { "r", "r", "rZ", "rZ" } }, + { INDEX_op_mulsh_i32, { "r", "rZ", "rZ" } }, + { INDEX_op_muluh_i32, { "r", "rZ", "rZ" } }, { INDEX_op_div_i32, { "r", "rZ", "rZ" } }, { INDEX_op_divu_i32, { "r", "rZ", "rZ" } }, { INDEX_op_rem_i32, { "r", "rZ", "rZ" } }, diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index 6cb7c2f..7ef79e0 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -89,8 +89,8 @@ typedef enum { #define TCG_TARGET_HAS_eqv_i32 0 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_muls2_i32 1 -#define TCG_TARGET_HAS_muluh_i32 0 -#define TCG_TARGET_HAS_mulsh_i32 0 +#define TCG_TARGET_HAS_muluh_i32 1 +#define TCG_TARGET_HAS_mulsh_i32 1 /* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */ #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ -- 1.8.1.4