[Qemu-devel] [PATCH v3 12/29] tcg-aarch64: Support andc, orc, eqv, not

[Richard Henderson <rth@twiddle.net>]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/aarch64/tcg-target.c | 65 ++++++++++++++++++++++++++++++++++++++++++------
 tcg/aarch64/tcg-target.h | 16 ++++++------
 2 files changed, 65 insertions(+), 16 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 9324185..eb080ed 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -253,10 +253,12 @@ typedef enum {
     INSN_EORI  = 0x52000000,
 
     /* Logical shifted register instructions */
-    INSN_AND    = 0x0a000000,
-    INSN_ORR    = 0x2a000000,
-    INSN_EOR    = 0x4a000000,
-    INSN_ANDS   = 0x6a000000,
+    INSN_AND   = 0x0a000000,
+    INSN_BIC   = 0x0a200000,
+    INSN_ORR   = 0x2a000000,
+    INSN_ORN   = 0x2a200000,
+    INSN_EOR   = 0x4a000000,
+    INSN_EON   = 0x4a200000,
 
     /* Add/subtract immediate instructions */
     INSN_ADDI  = 0x11000000,
@@ -265,10 +267,10 @@ typedef enum {
     INSN_SUBSI = 0x71000000,
 
     /* Add/subtract shifted register instructions */
-    INSN_ADD    = 0x0b000000,
-    INSN_ADDS   = 0x2b000000,
-    INSN_SUB    = 0x4b000000,
-    INSN_SUBS   = 0x6b000000,
+    INSN_ADD   = 0x0b000000,
+    INSN_ADDS  = 0x2b000000,
+    INSN_SUB   = 0x4b000000,
+    INSN_SUBS  = 0x6b000000,
 
     /* Data-processing (2 source) instructions */
     INSN_LSLV  = 0x1ac02000,
@@ -1250,6 +1252,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         }
         break;
 
+    case INDEX_op_andc_i32:
+        a2 = (int32_t)a2;
+        /* FALLTHRU */
+    case INDEX_op_andc_i64:
+        if (c2) {
+            tcg_fmt_Rdn_limm(s, INSN_ANDI, ext, a0, a1, ~a2);
+        } else {
+            tcg_fmt_Rdnm(s, INSN_BIC, ext, a0, a1, a2);
+        }
+        break;
+
     case INDEX_op_or_i32:
         a2 = (int32_t)a2;
         /* FALLTHRU */
@@ -1261,6 +1274,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         }
         break;
 
+    case INDEX_op_orc_i32:
+        a2 = (int32_t)a2;
+        /* FALLTHRU */
+    case INDEX_op_orc_i64:
+        if (c2) {
+            tcg_fmt_Rdn_limm(s, INSN_ORRI, ext, a0, a1, ~a2);
+        } else {
+            tcg_fmt_Rdnm(s, INSN_ORN, ext, a0, a1, a2);
+        }
+        break;
+
     case INDEX_op_xor_i32:
         a2 = (int32_t)a2;
         /* FALLTHRU */
@@ -1272,6 +1296,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         }
         break;
 
+    case INDEX_op_eqv_i32:
+        a2 = (int32_t)a2;
+        /* FALLTHRU */
+    case INDEX_op_eqv_i64:
+        if (c2) {
+            tcg_fmt_Rdn_limm(s, INSN_EORI, ext, a0, a1, ~a2);
+        } else {
+            tcg_fmt_Rdnm(s, INSN_EON, ext, a0, a1, a2);
+        }
+        break;
+
+    case INDEX_op_not_i64:
+    case INDEX_op_not_i32:
+        tcg_fmt_Rdnm(s, INSN_ORN, ext, a0, TCG_REG_XZR, a1);
+        break;
+
     case INDEX_op_mul_i64:
     case INDEX_op_mul_i32:
         tcg_out_mul(s, ext, a0, a1, a2);
@@ -1468,6 +1508,15 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
     { INDEX_op_or_i64, { "r", "r", "rL" } },
     { INDEX_op_xor_i32, { "r", "r", "rwL" } },
     { INDEX_op_xor_i64, { "r", "r", "rL" } },
+    { INDEX_op_andc_i32, { "r", "r", "rwL" } },
+    { INDEX_op_andc_i64, { "r", "r", "rL" } },
+    { INDEX_op_orc_i32, { "r", "r", "rwL" } },
+    { INDEX_op_orc_i64, { "r", "r", "rL" } },
+    { INDEX_op_eqv_i32, { "r", "r", "rwL" } },
+    { INDEX_op_eqv_i64, { "r", "r", "rL" } },
+
+    { INDEX_op_not_i32, { "r", "r" } },
+    { INDEX_op_not_i64, { "r", "r" } },
 
     { INDEX_op_shl_i32, { "r", "r", "ri" } },
     { INDEX_op_shr_i32, { "r", "r", "ri" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index 26ee28b..6242136 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -47,12 +47,12 @@ typedef enum {
 #define TCG_TARGET_HAS_ext16u_i32       1
 #define TCG_TARGET_HAS_bswap16_i32      1
 #define TCG_TARGET_HAS_bswap32_i32      1
-#define TCG_TARGET_HAS_not_i32          0
+#define TCG_TARGET_HAS_not_i32          1
 #define TCG_TARGET_HAS_neg_i32          0
 #define TCG_TARGET_HAS_rot_i32          1
-#define TCG_TARGET_HAS_andc_i32         0
-#define TCG_TARGET_HAS_orc_i32          0
-#define TCG_TARGET_HAS_eqv_i32          0
+#define TCG_TARGET_HAS_andc_i32         1
+#define TCG_TARGET_HAS_orc_i32          1
+#define TCG_TARGET_HAS_eqv_i32          1
 #define TCG_TARGET_HAS_nand_i32         0
 #define TCG_TARGET_HAS_nor_i32          0
 #define TCG_TARGET_HAS_deposit_i32      0
@@ -75,12 +75,12 @@ typedef enum {
 #define TCG_TARGET_HAS_bswap16_i64      1
 #define TCG_TARGET_HAS_bswap32_i64      1
 #define TCG_TARGET_HAS_bswap64_i64      1
-#define TCG_TARGET_HAS_not_i64          0
+#define TCG_TARGET_HAS_not_i64          1
 #define TCG_TARGET_HAS_neg_i64          0
 #define TCG_TARGET_HAS_rot_i64          1
-#define TCG_TARGET_HAS_andc_i64         0
-#define TCG_TARGET_HAS_orc_i64          0
-#define TCG_TARGET_HAS_eqv_i64          0
+#define TCG_TARGET_HAS_andc_i64         1
+#define TCG_TARGET_HAS_orc_i64          1
+#define TCG_TARGET_HAS_eqv_i64          1
 #define TCG_TARGET_HAS_nand_i64         0
 #define TCG_TARGET_HAS_nor_i64          0
 #define TCG_TARGET_HAS_deposit_i64      0
-- 
1.8.3.1