[Qemu-devel] [PATCH v3 15/29] tcg-aarch64: Support deposit

[Richard Henderson <rth@twiddle.net>]

Also tidy the implementation of ubfm, sbfm, extr in order to share code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/aarch64/tcg-target.c | 47 ++++++++++++++++++++++++++++++++++-------------
 tcg/aarch64/tcg-target.h |  4 ++--
 2 files changed, 36 insertions(+), 15 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 322660d..0dc3fee 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -285,6 +285,12 @@ typedef enum {
     INSN_ASRV  = 0x1ac02800,
     INSN_RORV  = 0x1ac02c00,
 
+    /* Bitfield instructions */
+    INSN_BFM   = 0x33000000,
+    INSN_SBFM  = 0x13000000,
+    INSN_UBFM  = 0x53000000,
+    INSN_EXTR  = 0x13800000,
+
     /* Conditional select instructions */
     INSN_CSEL  = 0x1a800000,
     INSN_CSINC = 0x1a800400,
@@ -593,28 +599,28 @@ static inline void tcg_out_mul(TCGContext *s, bool ext,
     tcg_out32(s, base | rm << 16 | rn << 5 | rd);
 }
 
+static inline void tcg_out_bfm(TCGContext *s, bool ext, TCGReg rd, TCGReg rn,
+                               unsigned int a, unsigned int b)
+{
+    tcg_fmt_Rdn_r_s(s, INSN_BFM, ext, rd, rn, a, b);
+}
+
 static inline void tcg_out_ubfm(TCGContext *s, bool ext, TCGReg rd, TCGReg rn,
                                 unsigned int a, unsigned int b)
 {
-    /* Using UBFM 0x53000000 Wd, Wn, a, b */
-    unsigned int base = ext ? 0xd3400000 : 0x53000000;
-    tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd);
+    tcg_fmt_Rdn_r_s(s, INSN_UBFM, ext, rd, rn, a, b);
 }
 
 static inline void tcg_out_sbfm(TCGContext *s, bool ext, TCGReg rd, TCGReg rn,
                                 unsigned int a, unsigned int b)
 {
-    /* Using SBFM 0x13000000 Wd, Wn, a, b */
-    unsigned int base = ext ? 0x93400000 : 0x13000000;
-    tcg_out32(s, base | a << 16 | b << 10 | rn << 5 | rd);
+    tcg_fmt_Rdn_r_s(s, INSN_SBFM, ext, rd, rn, a, b);
 }
 
 static inline void tcg_out_extr(TCGContext *s, bool ext, TCGReg rd,
                                 TCGReg rn, TCGReg rm, unsigned int a)
 {
-    /* Using EXTR 0x13800000 Wd, Wn, Wm, a */
-    unsigned int base = ext ? 0x93c00000 : 0x13800000;
-    tcg_out32(s, base | rm << 16 | a << 10 | rn << 5 | rd);
+    tcg_fmt_Rdn_r_s(s, INSN_EXTR, ext, rd, rn, a, rm);
 }
 
 static inline void tcg_out_shl(TCGContext *s, bool ext,
@@ -656,6 +662,15 @@ static inline void tcg_out_rotl(TCGContext *s, bool ext,
     tcg_out_extr(s, ext, rd, rn, rn, bits - (m & max));
 }
 
+static inline void tcg_out_dep(TCGContext *s, bool ext, TCGReg rd, TCGReg rn,
+                               unsigned lsb, unsigned width)
+{
+    unsigned size = ext ? 64 : 32;
+    unsigned a = (size - lsb) & (size - 1);
+    unsigned b = width - 1;
+    tcg_out_bfm(s, ext, rd, rn, a, b);
+}
+
 static void tcg_out_cmp(TCGContext *s, bool ext, TCGReg a,
                         tcg_target_long b, bool const_b)
 {
@@ -809,8 +824,7 @@ static inline void tcg_out_rev16(TCGContext *s, bool ext, TCGReg rd, TCGReg rm)
 static inline void tcg_out_sxt(TCGContext *s, bool ext, int s_bits,
                                TCGReg rd, TCGReg rn)
 {
-    /* using ALIASes SXTB 0x13001c00, SXTH 0x13003c00, SXTW 0x93407c00
-       of SBFM Xd, Xn, #0, #7|15|31 */
+    /* Using ALIASes SXTB, SXTH, SXTW, of SBFM Xd, Xn, #0, #7|15|31 */
     int bits = 8 * (1 << s_bits) - 1;
     tcg_out_sbfm(s, ext, rd, rn, 0, bits);
 }
@@ -818,8 +832,7 @@ static inline void tcg_out_sxt(TCGContext *s, bool ext, int s_bits,
 static inline void tcg_out_uxt(TCGContext *s, int s_bits,
                                TCGReg rd, TCGReg rn)
 {
-    /* using ALIASes UXTB 0x53001c00, UXTH 0x53003c00
-       of UBFM Wd, Wn, #0, #7|15 */
+    /* Using ALIASes UXTB, UXTH of UBFM Wd, Wn, #0, #7|15 */
     int bits = 8 * (1 << s_bits) - 1;
     tcg_out_ubfm(s, 0, rd, rn, 0, bits);
 }
@@ -1485,6 +1498,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         tcg_out_movr(s, 0, a0, a1);
         break;
 
+    case INDEX_op_deposit_i64:
+    case INDEX_op_deposit_i32:
+        tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]);
+        break;
+
     case INDEX_op_mov_i64:
     case INDEX_op_mov_i32:
     case INDEX_op_movi_i64:
@@ -1604,6 +1622,9 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
     { INDEX_op_ext16u_i64, { "r", "r" } },
     { INDEX_op_ext32u_i64, { "r", "r" } },
 
+    { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
+    { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
+
     { -1 },
 };
 
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index ff073ca..712e4e7 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -55,7 +55,7 @@ typedef enum {
 #define TCG_TARGET_HAS_eqv_i32          1
 #define TCG_TARGET_HAS_nand_i32         0
 #define TCG_TARGET_HAS_nor_i32          0
-#define TCG_TARGET_HAS_deposit_i32      0
+#define TCG_TARGET_HAS_deposit_i32      1
 #define TCG_TARGET_HAS_movcond_i32      1
 #define TCG_TARGET_HAS_add2_i32         0
 #define TCG_TARGET_HAS_sub2_i32         0
@@ -83,7 +83,7 @@ typedef enum {
 #define TCG_TARGET_HAS_eqv_i64          1
 #define TCG_TARGET_HAS_nand_i64         0
 #define TCG_TARGET_HAS_nor_i64          0
-#define TCG_TARGET_HAS_deposit_i64      0
+#define TCG_TARGET_HAS_deposit_i64      1
 #define TCG_TARGET_HAS_movcond_i64      1
 #define TCG_TARGET_HAS_add2_i64         0
 #define TCG_TARGET_HAS_sub2_i64         0
-- 
1.8.3.1