From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56769) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGYLq-00064B-Dn for qemu-devel@nongnu.org; Mon, 02 Sep 2013 13:55:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGYLk-0001BT-43 for qemu-devel@nongnu.org; Mon, 02 Sep 2013 13:55:46 -0400 Received: from mail-pd0-x22e.google.com ([2607:f8b0:400e:c02::22e]:36499) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGYLj-0001BF-59 for qemu-devel@nongnu.org; Mon, 02 Sep 2013 13:55:40 -0400 Received: by mail-pd0-f174.google.com with SMTP id y13so5004145pdi.19 for ; Mon, 02 Sep 2013 10:55:38 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 2 Sep 2013 10:54:52 -0700 Message-Id: <1378144503-15808-19-git-send-email-rth@twiddle.net> In-Reply-To: <1378144503-15808-1-git-send-email-rth@twiddle.net> References: <1378144503-15808-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v3 18/29] tcg-aarch64: Support div, rem List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: claudio.fontana@huawei.com, Richard Henderson For remainder, generic code will produce mul+sub, whereas we can implement with msub. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 50 +++++++++++++++++++++++++++++++++++++++--------- tcg/aarch64/tcg-target.h | 8 ++++---- 2 files changed, 45 insertions(+), 13 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index 5ab0596..09ccd67 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -297,6 +297,12 @@ typedef enum { INSN_RORV = 0x1ac02c00, INSN_SMULH = 0x9b407c00, INSN_UMULH = 0x9bc07c00, + INSN_UDIV = 0x1ac00800, + INSN_SDIV = 0x1ac00c00, + + /* Data-processing (3 source) instructions */ + INSN_MADD = 0x1b000000, + INSN_MSUB = 0x1b008000, /* Bitfield instructions */ INSN_BFM = 0x33000000, @@ -398,6 +404,12 @@ static inline void tcg_fmt_Rdnm(TCGContext *s, AArch64Insn insn, bool ext, tcg_out32(s, insn | ext << 31 | rm << 16 | rn << 5 | rd); } +static inline void tcg_fmt_Rdnma(TCGContext *s, AArch64Insn insn, bool ext, + TCGReg rd, TCGReg rn, TCGReg rm, TCGReg ra) +{ + tcg_out32(s, insn | ext << 31 | rm << 16 | ra << 10 | rn << 5 | rd); +} + static inline void tcg_fmt_Rdnm_shift(TCGContext *s, AArch64Insn insn, bool ext, TCGReg rd, TCGReg rn, TCGReg rm, int shift_imm) @@ -604,14 +616,6 @@ static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, arg, arg1, arg2); } -static inline void tcg_out_mul(TCGContext *s, bool ext, - TCGReg rd, TCGReg rn, TCGReg rm) -{ - /* Using MADD 0x1b000000 with Ra = wzr alias MUL 0x1b007c00 */ - unsigned int base = ext ? 0x9b007c00 : 0x1b007c00; - tcg_out32(s, base | rm << 16 | rn << 5 | rd); -} - static inline void tcg_out_bfm(TCGContext *s, bool ext, TCGReg rd, TCGReg rn, unsigned int a, unsigned int b) { @@ -1404,7 +1408,27 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_mul_i64: case INDEX_op_mul_i32: - tcg_out_mul(s, ext, a0, a1, a2); + tcg_fmt_Rdnma(s, INSN_MADD, ext, a0, a1, a2, TCG_REG_XZR); + break; + + case INDEX_op_div_i64: + case INDEX_op_div_i32: + tcg_fmt_Rdnm(s, INSN_SDIV, ext, a0, a1, a2); + break; + case INDEX_op_divu_i64: + case INDEX_op_divu_i32: + tcg_fmt_Rdnm(s, INSN_UDIV, ext, a0, a1, a2); + break; + + case INDEX_op_rem_i64: + case INDEX_op_rem_i32: + tcg_fmt_Rdnm(s, INSN_SDIV, ext, TCG_REG_TMP, a1, a2); + tcg_fmt_Rdnma(s, INSN_MSUB, ext, a0, TCG_REG_TMP, a2, a1); + break; + case INDEX_op_remu_i64: + case INDEX_op_remu_i32: + tcg_fmt_Rdnm(s, INSN_UDIV, ext, TCG_REG_TMP, a1, a2); + tcg_fmt_Rdnma(s, INSN_MSUB, ext, a0, TCG_REG_TMP, a2, a1); break; case INDEX_op_shl_i64: @@ -1637,6 +1661,14 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_sub_i64, { "r", "rZ", "rA" } }, { INDEX_op_mul_i32, { "r", "r", "r" } }, { INDEX_op_mul_i64, { "r", "r", "r" } }, + { INDEX_op_div_i32, { "r", "r", "r" } }, + { INDEX_op_div_i64, { "r", "r", "r" } }, + { INDEX_op_divu_i32, { "r", "r", "r" } }, + { INDEX_op_divu_i64, { "r", "r", "r" } }, + { INDEX_op_rem_i32, { "r", "r", "r" } }, + { INDEX_op_rem_i64, { "r", "r", "r" } }, + { INDEX_op_remu_i32, { "r", "r", "r" } }, + { INDEX_op_remu_i64, { "r", "r", "r" } }, { INDEX_op_and_i32, { "r", "r", "rwL" } }, { INDEX_op_and_i64, { "r", "r", "rL" } }, { INDEX_op_or_i32, { "r", "r", "rwL" } }, diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index 8fd6771..bf72e62 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -39,8 +39,8 @@ typedef enum { #define TCG_TARGET_CALL_STACK_OFFSET 0 /* optional instructions */ -#define TCG_TARGET_HAS_div_i32 0 -#define TCG_TARGET_HAS_rem_i32 0 +#define TCG_TARGET_HAS_div_i32 1 +#define TCG_TARGET_HAS_rem_i32 1 #define TCG_TARGET_HAS_ext8s_i32 1 #define TCG_TARGET_HAS_ext16s_i32 1 #define TCG_TARGET_HAS_ext8u_i32 1 @@ -64,8 +64,8 @@ typedef enum { #define TCG_TARGET_HAS_muluh_i32 0 #define TCG_TARGET_HAS_mulsh_i32 0 -#define TCG_TARGET_HAS_div_i64 0 -#define TCG_TARGET_HAS_rem_i64 0 +#define TCG_TARGET_HAS_div_i64 1 +#define TCG_TARGET_HAS_rem_i64 1 #define TCG_TARGET_HAS_ext8s_i64 1 #define TCG_TARGET_HAS_ext16s_i64 1 #define TCG_TARGET_HAS_ext32s_i64 1 -- 1.8.3.1