From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56583) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGYLU-0005l1-Vk for qemu-devel@nongnu.org; Mon, 02 Sep 2013 13:55:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGYLP-000160-5Z for qemu-devel@nongnu.org; Mon, 02 Sep 2013 13:55:24 -0400 Received: from mail-pd0-x234.google.com ([2607:f8b0:400e:c02::234]:37914) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGYLO-00015n-Nw for qemu-devel@nongnu.org; Mon, 02 Sep 2013 13:55:19 -0400 Received: by mail-pd0-f180.google.com with SMTP id y10so4991344pdj.11 for ; Mon, 02 Sep 2013 10:55:17 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Mon, 2 Sep 2013 10:54:40 -0700 Message-Id: <1378144503-15808-7-git-send-email-rth@twiddle.net> In-Reply-To: <1378144503-15808-1-git-send-email-rth@twiddle.net> References: <1378144503-15808-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v3 06/29] tcg-aarch64: Merge enum aarch64_srr_opc with AArch64Insn List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: claudio.fontana@huawei.com, Richard Henderson And since we're no longer talking about opcodes, merge the 0x1ac02000 data2 primary opcode with the shift subcode to create the full insn. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 49 ++++++++++++++++++++++++------------------------ 1 file changed, 24 insertions(+), 25 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index d1ca402..de97fbd 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -211,14 +211,13 @@ typedef enum { INSN_ADDS = 0x2b000000, INSN_SUB = 0x4b000000, INSN_SUBS = 0x6b000000, -} AArch64Insn; -enum aarch64_srr_opc { - SRR_SHL = 0x0, - SRR_SHR = 0x4, - SRR_SAR = 0x8, - SRR_ROR = 0xc -}; + /* Data-processing (2 source) instructions */ + INSN_LSLV = 0x1ac02000, + INSN_LSRV = 0x1ac02400, + INSN_ASRV = 0x1ac02800, + INSN_RORV = 0x1ac02c00, +} AArch64Insn; static inline enum aarch64_ldst_op_data aarch64_ldst_get_data(TCGOpcode tcg_op) @@ -465,12 +464,12 @@ static inline void tcg_out_mul(TCGContext *s, bool ext, } static inline void tcg_out_shiftrot_reg(TCGContext *s, - enum aarch64_srr_opc opc, bool ext, + AArch64Insn insn, bool ext, TCGReg rd, TCGReg rn, TCGReg rm) { /* using 2-source data processing instructions 0x1ac02000 */ - unsigned int base = ext ? 0x9ac02000 : 0x1ac02000; - tcg_out32(s, base | rm << 16 | opc << 8 | rn << 5 | rd); + unsigned int base = insn | (ext ? 0x80000000 : 0); + tcg_out32(s, base | rm << 16 | rn << 5 | rd); } static inline void tcg_out_ubfm(TCGContext *s, bool ext, TCGReg rd, TCGReg rn, @@ -1204,47 +1203,47 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, case INDEX_op_shl_i64: case INDEX_op_shl_i32: - if (c2) { /* LSL / UBFM Wd, Wn, (32 - m) */ + if (c2) { tcg_out_shl(s, ext, a0, a1, a2); - } else { /* LSL / LSLV */ - tcg_out_shiftrot_reg(s, SRR_SHL, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_LSLV, ext, a0, a1, a2); } break; case INDEX_op_shr_i64: case INDEX_op_shr_i32: - if (c2) { /* LSR / UBFM Wd, Wn, m, 31 */ + if (c2) { tcg_out_shr(s, ext, a0, a1, a2); - } else { /* LSR / LSRV */ - tcg_out_shiftrot_reg(s, SRR_SHR, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_LSRV, ext, a0, a1, a2); } break; case INDEX_op_sar_i64: case INDEX_op_sar_i32: - if (c2) { /* ASR / SBFM Wd, Wn, m, 31 */ + if (c2) { tcg_out_sar(s, ext, a0, a1, a2); - } else { /* ASR / ASRV */ - tcg_out_shiftrot_reg(s, SRR_SAR, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_ASRV, ext, a0, a1, a2); } break; case INDEX_op_rotr_i64: case INDEX_op_rotr_i32: - if (c2) { /* ROR / EXTR Wd, Wm, Wm, m */ + if (c2) { tcg_out_rotr(s, ext, a0, a1, a2); - } else { /* ROR / RORV */ - tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, a2); + } else { + tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, a2); } break; case INDEX_op_rotl_i64: - case INDEX_op_rotl_i32: /* same as rotate right by (32 - m) */ - if (c2) { /* ROR / EXTR Wd, Wm, Wm, 32 - m */ + case INDEX_op_rotl_i32: + if (c2) { tcg_out_rotl(s, ext, a0, a1, a2); } else { tcg_out_arith(s, INSN_SUB, 0, TCG_REG_TMP, TCG_REG_XZR, a2, 0); - tcg_out_shiftrot_reg(s, SRR_ROR, ext, a0, a1, TCG_REG_TMP); + tcg_out_shiftrot_reg(s, INSN_RORV, ext, a0, a1, TCG_REG_TMP); } break; -- 1.8.3.1