From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:52798) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGt7p-0003gP-9C for qemu-devel@nongnu.org; Tue, 03 Sep 2013 12:06:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGt7j-0006n6-Tb for qemu-devel@nongnu.org; Tue, 03 Sep 2013 12:06:41 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43531 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGt7j-0006mv-ND for qemu-devel@nongnu.org; Tue, 03 Sep 2013 12:06:35 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 3 Sep 2013 18:06:24 +0200 Message-Id: <1378224387-18760-2-git-send-email-afaerber@suse.de> In-Reply-To: <1378224387-18760-1-git-send-email-afaerber@suse.de> References: <1378224387-18760-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 1/4] a15mpcore: Use qemu_get_cpu() for generic timers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook This simplifies the loop and aids with refactoring of CPU list. Requested-by: Peter Maydell Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/a15mpcore.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index af182da..9abba67 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -50,7 +50,6 @@ static int a15mp_priv_init(SysBusDevice *dev) SysBusDevice *busdev; const char *gictype =3D "arm_gic"; int i; - CPUState *cpu; =20 if (kvm_irqchip_in_kernel()) { gictype =3D "kvm-arm-gic"; @@ -72,8 +71,8 @@ static int a15mp_priv_init(SysBusDevice *dev) /* Wire the outputs from each CPU's generic timer to the * appropriate GIC PPI inputs */ - for (i =3D 0, cpu =3D first_cpu; i < s->num_cpu; i++, cpu =3D cpu->n= ext_cpu) { - DeviceState *cpudev =3D DEVICE(cpu); + for (i =3D 0; i < s->num_cpu; i++) { + DeviceState *cpudev =3D DEVICE(qemu_get_cpu(i)); int ppibase =3D s->num_irq - 32 + i * 32; /* physical timer; we wire it up to the non-secure timer's ID, * since a real A15 always has TrustZone but QEMU doesn't. --=20 1.8.1.4