From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42051) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGw1l-0005Yo-Se for qemu-devel@nongnu.org; Tue, 03 Sep 2013 15:12:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGw1a-0007yS-Ku for qemu-devel@nongnu.org; Tue, 03 Sep 2013 15:12:37 -0400 Received: from v6.chiark.greenend.org.uk ([2001:ba8:1e3::]:38401 helo=chiark.greenend.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGw1a-0007wv-Bx for qemu-devel@nongnu.org; Tue, 03 Sep 2013 15:12:26 -0400 From: Peter Maydell Date: Tue, 3 Sep 2013 20:12:03 +0100 Message-Id: <1378235544-22290-4-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1378235544-22290-1-git-send-email-peter.maydell@linaro.org> References: <1378235544-22290-1-git-send-email-peter.maydell@linaro.org> Sender: Peter Maydell Subject: [Qemu-devel] [PATCH v6 03/24] target-arm: Extract the disas struct to a header file List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Mian M. Hamayun" , patches@linaro.org, Andreas Schwab , Alexander Graf , kvmarm@lists.cs.columbia.edu, =?UTF-8?q?Andreas=20F=C3=A4rber?= From: Alexander Graf We will need to share the disassembly status struct between AArch32 and AArch64 modes. So put it into a header file that both sides can use. Signed-off-by: Alexander Graf Signed-off-by: John Rigby Message-id: 1368505980-17151-2-git-send-email-john.rigby@linaro.org Signed-off-by: Peter Maydell --- target-arm/translate.c | 24 +----------------------- target-arm/translate.h | 27 +++++++++++++++++++++++++++ 2 files changed, 28 insertions(+), 23 deletions(-) create mode 100644 target-arm/translate.h diff --git a/target-arm/translate.c b/target-arm/translate.c index 8e58eb1..1bb6f46 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -46,29 +46,7 @@ #define ARCH(x) do { if (!ENABLE_ARCH_##x) goto illegal_op; } while(0) -/* internal defines */ -typedef struct DisasContext { - target_ulong pc; - int is_jmp; - /* Nonzero if this instruction has been conditionally skipped. */ - int condjmp; - /* The label that will be jumped to when the instruction is skipped. */ - int condlabel; - /* Thumb-2 conditional execution bits. */ - int condexec_mask; - int condexec_cond; - struct TranslationBlock *tb; - int singlestep_enabled; - int thumb; - int bswap_code; -#if !defined(CONFIG_USER_ONLY) - int user; -#endif - int vfp_enabled; - int vec_len; - int vec_stride; -} DisasContext; - +#include "translate.h" static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE]; #if defined(CONFIG_USER_ONLY) diff --git a/target-arm/translate.h b/target-arm/translate.h new file mode 100644 index 0000000..e727bc6 --- /dev/null +++ b/target-arm/translate.h @@ -0,0 +1,27 @@ +#ifndef TARGET_ARM_TRANSLATE_H +#define TARGET_ARM_TRANSLATE_H + +/* internal defines */ +typedef struct DisasContext { + target_ulong pc; + int is_jmp; + /* Nonzero if this instruction has been conditionally skipped. */ + int condjmp; + /* The label that will be jumped to when the instruction is skipped. */ + int condlabel; + /* Thumb-2 conditional execution bits. */ + int condexec_mask; + int condexec_cond; + struct TranslationBlock *tb; + int singlestep_enabled; + int thumb; + int bswap_code; +#if !defined(CONFIG_USER_ONLY) + int user; +#endif + int vfp_enabled; + int vec_len; + int vec_stride; +} DisasContext; + +#endif /* TARGET_ARM_TRANSLATE_H */ -- 1.7.9.5