From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:42008) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGw1k-0005Yc-H0 for qemu-devel@nongnu.org; Tue, 03 Sep 2013 15:12:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGw1a-0007xn-JE for qemu-devel@nongnu.org; Tue, 03 Sep 2013 15:12:36 -0400 Received: from v6.chiark.greenend.org.uk ([2001:ba8:1e3::]:38403 helo=chiark.greenend.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGw1a-0007x0-Af for qemu-devel@nongnu.org; Tue, 03 Sep 2013 15:12:26 -0400 From: Peter Maydell Date: Tue, 3 Sep 2013 20:12:05 +0100 Message-Id: <1378235544-22290-6-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1378235544-22290-1-git-send-email-peter.maydell@linaro.org> References: <1378235544-22290-1-git-send-email-peter.maydell@linaro.org> Sender: Peter Maydell Subject: [Qemu-devel] [PATCH v6 05/24] target-arm: Fix target_ulong/uint32_t confusions List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: "Mian M. Hamayun" , patches@linaro.org, Andreas Schwab , Alexander Graf , kvmarm@lists.cs.columbia.edu, =?UTF-8?q?Andreas=20F=C3=A4rber?= From: Alexander Graf Correct a few places that were using uint32_t or a 32 bit only format string to handle something that should be a target_ulong. Signed-off-by: Alexander Graf Signed-off-by: John Rigby [PMM: split out to separate patch; added gen_goto_tb() and gen_set_pc_im() dest params to list of things to change.] Signed-off-by: Peter Maydell --- target-arm/cpu.h | 4 ++-- target-arm/translate.c | 9 +++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index f2abdf3..8d1cc47 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -823,7 +823,7 @@ static inline bool cpu_has_work(CPUState *cpu) #include "exec/exec-all.h" /* Load an instruction and return it in the standard little-endian order */ -static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr, +static inline uint32_t arm_ldl_code(CPUARMState *env, target_ulong addr, bool do_swap) { uint32_t insn = cpu_ldl_code(env, addr); @@ -834,7 +834,7 @@ static inline uint32_t arm_ldl_code(CPUARMState *env, uint32_t addr, } /* Ditto, for a halfword (Thumb) instruction */ -static inline uint16_t arm_lduw_code(CPUARMState *env, uint32_t addr, +static inline uint16_t arm_lduw_code(CPUARMState *env, target_ulong addr, bool do_swap) { uint16_t insn = cpu_lduw_code(env, addr); diff --git a/target-arm/translate.c b/target-arm/translate.c index a6adcc8..5a465fc 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -904,7 +904,7 @@ DO_GEN_ST(st8) DO_GEN_ST(st16) DO_GEN_ST(st32) -static inline void gen_set_pc_im(uint32_t val) +static inline void gen_set_pc_im(target_ulong val) { tcg_gen_movi_i32(cpu_R[15], val); } @@ -3412,7 +3412,7 @@ static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn) return 0; } -static inline void gen_goto_tb(DisasContext *s, int n, uint32_t dest) +static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest) { TranslationBlock *tb; @@ -9992,7 +9992,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, uint16_t *gen_opc_end; int j, lj; target_ulong pc_start; - uint32_t next_page_start; + target_ulong next_page_start; int num_insns; int max_insns; @@ -10146,7 +10146,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, } if (tcg_check_temp_count()) { - fprintf(stderr, "TCG temporary leak before %08x\n", dc->pc); + fprintf(stderr, "TCG temporary leak before "TARGET_FMT_lx"\n", + dc->pc); } /* Translation stops when a conditional branch is encountered. -- 1.7.9.5