From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34819) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VGz5N-0007ld-It for qemu-devel@nongnu.org; Tue, 03 Sep 2013 18:28:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VGz5I-0005eL-0H for qemu-devel@nongnu.org; Tue, 03 Sep 2013 18:28:33 -0400 From: =?UTF-8?q?Herv=C3=A9=20Poussineau?= Date: Wed, 4 Sep 2013 00:29:08 +0200 Message-Id: <1378247351-8446-9-git-send-email-hpoussin@reactos.org> In-Reply-To: <1378247351-8446-1-git-send-email-hpoussin@reactos.org> References: <1378247351-8446-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PATCH v2 08/10] raven: implement non-contiguous I/O region List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Herv=C3=A9=20Poussineau?= , =?UTF-8?q?=20Andreas=20F=C3=A4rber?= , qemu-ppc@nongnu.org Remove now duplicated code from prep board. Signed-off-by: Herv=C3=A9 Poussineau --- hw/pci-host/prep.c | 82 +++++++++++++++++++++++++++++++++++++++++++++ hw/ppc/prep.c | 94 ++--------------------------------------------= ------ 2 files changed, 85 insertions(+), 91 deletions(-) diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 3baf66f..db03adc 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -53,7 +53,9 @@ typedef struct PRePPCIState { =20 qemu_irq irq[PCI_NUM_PINS]; PCIBus pci_bus; + AddressSpace pci_io_as; MemoryRegion pci_io; + MemoryRegion pci_io_non_contiguous; MemoryRegion pci_memory; MemoryRegion pci_intack; MemoryRegion bm; @@ -61,6 +63,8 @@ typedef struct PRePPCIState { MemoryRegion bm_pci_memory_alias; AddressSpace bm_as; RavenPCIState pci_dev; + + int contiguous_map; } PREPPCIState; =20 #define BIOS_SIZE (1024 * 1024) @@ -112,6 +116,71 @@ static const MemoryRegionOps PPC_intack_ops =3D { }, }; =20 +static inline hwaddr raven_io_address(PREPPCIState *s, + hwaddr addr) +{ + if (s->contiguous_map =3D=3D 0) { + /* 64 KB contiguous space for IOs */ + addr &=3D 0xFFFF; + } else { + /* 8 MB non-contiguous space for IOs */ + addr =3D (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); + } + + /* FIXME: handle endianness switch */ + + return addr; +} + +static uint64_t raven_io_read(void *opaque, hwaddr addr, + unsigned int size) +{ + PREPPCIState *s =3D opaque; + uint8_t buf[4]; + + addr =3D raven_io_address(s, addr); + address_space_read(&s->pci_io_as, addr + 0x80000000, buf, size); + + if (size =3D=3D 1) { + return buf[0]; + } else if (size =3D=3D 2) { + return lduw_p(buf); + } else if (size =3D=3D 4) { + return ldl_p(buf); + } else { + assert(false); + } +} + +static void raven_io_write(void *opaque, hwaddr addr, + uint64_t val, unsigned int size) +{ + PREPPCIState *s =3D opaque; + uint8_t buf[4]; + + addr =3D raven_io_address(s, addr); + + if (size =3D=3D 1) { + buf[0] =3D val; + } else if (size =3D=3D 2) { + stw_p(buf, val); + } else if (size =3D=3D 4) { + stl_p(buf, val); + } else { + assert(false); + } + + address_space_write(&s->pci_io_as, addr + 0x80000000, buf, size); +} + +static const MemoryRegionOps raven_io_ops =3D { + .read =3D raven_io_read, + .write =3D raven_io_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .impl.max_access_size =3D 4, + .valid.unaligned =3D true, +}; + static int prep_map_irq(PCIDevice *pci_dev, int irq_num) { return (irq_num + (pci_dev->devfn >> 3)) & 1; @@ -131,6 +200,12 @@ static AddressSpace *raven_pcihost_set_iommu(PCIBus = *bus, void *opaque, return &s->bm_as; } =20 +static void raven_change_gpio(void *opaque, int n, int level) +{ + PREPPCIState *s =3D opaque; + s->contiguous_map =3D level; +} + static void raven_pcihost_realizefn(DeviceState *d, Error **errp) { SysBusDevice *dev =3D SYS_BUS_DEVICE(d); @@ -143,6 +218,8 @@ static void raven_pcihost_realizefn(DeviceState *d, E= rror **errp) sysbus_init_irq(dev, &s->irq[i]); } =20 + qdev_init_gpio_in(d, raven_change_gpio, 1); + pci_bus_irqs(&s->pci_bus, prep_set_irq, prep_map_irq, s->irq, PCI_NU= M_PINS); =20 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops= , s, @@ -172,12 +249,17 @@ static void raven_pcihost_initfn(Object *obj) DeviceState *pci_dev; =20 memory_region_init(&s->pci_io, obj, "pci-io", 0x3f800000); + memory_region_init_io(&s->pci_io_non_contiguous, obj, &raven_io_ops,= s, + "pci-io-non-contiguous", 0x00800000); /* Open Hack'Ware hack: real size should be only 0x3f000000 bytes */ memory_region_init(&s->pci_memory, obj, "pci-memory", 0x3f000000 + 0xc0000000ULL); + address_space_init(&s->pci_io_as, &s->pci_io, "raven-io"); =20 /* CPU address space */ memory_region_add_subregion(address_space_mem, 0x80000000, &s->pci_i= o); + memory_region_add_subregion_overlap(address_space_mem, 0x80000000, + &s->pci_io_non_contiguous, 1); memory_region_add_subregion(address_space_mem, 0xc0000000, &s->pci_m= emory); pci_bus_new_inplace(&s->pci_bus, DEVICE(obj), NULL, &s->pci_memory, &s->pci_io, 0, TYPE_PCI_BUS); diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index e75c4f0..70132a6 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -185,6 +185,7 @@ typedef struct sysctrl_t { uint8_t state; uint8_t syscontrol; int contiguous_map; + qemu_irq contiguous_map_irq; int endian; } sysctrl_t; =20 @@ -253,6 +254,7 @@ static void PREP_io_800_writeb (void *opaque, uint32_= t addr, uint32_t val) case 0x0850: /* I/O map type register */ sysctrl->contiguous_map =3D val & 0x01; + qemu_set_irq(sysctrl->contiguous_map_irq, sysctrl->contiguous_ma= p); break; default: printf("ERROR: unaffected IO port write: %04" PRIx32 @@ -327,91 +329,6 @@ static uint32_t PREP_io_800_readb (void *opaque, uin= t32_t addr) return retval; } =20 -static inline hwaddr prep_IO_address(sysctrl_t *sysctrl, - hwaddr addr) -{ - if (sysctrl->contiguous_map =3D=3D 0) { - /* 64 KB contiguous space for IOs */ - addr &=3D 0xFFFF; - } else { - /* 8 MB non-contiguous space for IOs */ - addr =3D (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); - } - - return addr; -} - -static void PPC_prep_io_writeb (void *opaque, hwaddr addr, - uint32_t value) -{ - sysctrl_t *sysctrl =3D opaque; - - addr =3D prep_IO_address(sysctrl, addr); - cpu_outb(addr, value); -} - -static uint32_t PPC_prep_io_readb (void *opaque, hwaddr addr) -{ - sysctrl_t *sysctrl =3D opaque; - uint32_t ret; - - addr =3D prep_IO_address(sysctrl, addr); - ret =3D cpu_inb(addr); - - return ret; -} - -static void PPC_prep_io_writew (void *opaque, hwaddr addr, - uint32_t value) -{ - sysctrl_t *sysctrl =3D opaque; - - addr =3D prep_IO_address(sysctrl, addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " =3D> 0x%08" PRIx32 "\n", addr, = value); - cpu_outw(addr, value); -} - -static uint32_t PPC_prep_io_readw (void *opaque, hwaddr addr) -{ - sysctrl_t *sysctrl =3D opaque; - uint32_t ret; - - addr =3D prep_IO_address(sysctrl, addr); - ret =3D cpu_inw(addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <=3D 0x%08" PRIx32 "\n", addr, = ret); - - return ret; -} - -static void PPC_prep_io_writel (void *opaque, hwaddr addr, - uint32_t value) -{ - sysctrl_t *sysctrl =3D opaque; - - addr =3D prep_IO_address(sysctrl, addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " =3D> 0x%08" PRIx32 "\n", addr, = value); - cpu_outl(addr, value); -} - -static uint32_t PPC_prep_io_readl (void *opaque, hwaddr addr) -{ - sysctrl_t *sysctrl =3D opaque; - uint32_t ret; - - addr =3D prep_IO_address(sysctrl, addr); - ret =3D cpu_inl(addr); - PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <=3D 0x%08" PRIx32 "\n", addr, = ret); - - return ret; -} - -static const MemoryRegionOps PPC_prep_io_ops =3D { - .old_mmio =3D { - .read =3D { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_re= adl }, - .write =3D { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io= _writel }, - }, - .endianness =3D DEVICE_NATIVE_ENDIAN, -}; =20 #define NVRAM_SIZE 0x2000 =20 @@ -458,7 +375,6 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) CPUPPCState *env =3D NULL; nvram_t nvram; M48t59State *m48t59; - MemoryRegion *PPC_io_memory =3D g_new(MemoryRegion, 1); PortioList *port_list =3D g_new(PortioList, 1); #if 0 MemoryRegion *xcsr =3D g_new(MemoryRegion, 1); @@ -578,6 +494,7 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) fprintf(stderr, "Couldn't create PCI host controller.\n"); exit(1); } + sysctrl->contiguous_map_irq =3D qdev_get_gpio_in(dev, 0); =20 /* PCI -> ISA bridge */ pci =3D pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378"); @@ -598,11 +515,6 @@ static void ppc_prep_init(QEMUMachineInitArgs *args) qdev_prop_set_uint8(dev, "config", 13); /* fdc, ser0, ser1, par0 */ qdev_init_nofail(dev); =20 - /* Register 8 MB of ISA IO space (needed for non-contiguous map) */ - memory_region_init_io(PPC_io_memory, NULL, &PPC_prep_io_ops, sysctrl= , - "ppc-io", 0x00800000); - memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory); - /* init basic PC hardware */ pci_vga_init(pci_bus); /* Open Hack'Ware hack: PCI BAR#0 is programmed to 0xf0000000. --=20 1.7.10.4