From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49751) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VH927-0004V2-FR for qemu-devel@nongnu.org; Wed, 04 Sep 2013 05:06:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VH920-0007vl-GR for qemu-devel@nongnu.org; Wed, 04 Sep 2013 05:05:51 -0400 Received: from cantor2.suse.de ([195.135.220.15]:45425 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VH920-0007vR-7N for qemu-devel@nongnu.org; Wed, 04 Sep 2013 05:05:44 -0400 Received: from relay2.suse.de (unknown [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id AA198A5429 for ; Wed, 4 Sep 2013 11:05:43 +0200 (CEST) From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 4 Sep 2013 11:04:57 +0200 Message-Id: <1378285521-3230-18-git-send-email-afaerber@suse.de> In-Reply-To: <1378285521-3230-1-git-send-email-afaerber@suse.de> References: <1378285521-3230-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [RFC qom-cpu 17/41] cpu: Move tlb_flush_{addr, mask} fields from CPU_COMMON_TLB to CPUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: =?UTF-8?q?Andreas=20F=C3=A4rber?= Change their type to vaddr but keep comparing target_ulongs for now. Signed-off-by: Andreas F=C3=A4rber --- cputlb.c | 27 ++++++++++++++------------- include/exec/cpu-defs.h | 2 -- include/qom/cpu.h | 3 +++ 3 files changed, 17 insertions(+), 15 deletions(-) diff --git a/cputlb.c b/cputlb.c index e8131d8..e02663c 100644 --- a/cputlb.c +++ b/cputlb.c @@ -74,8 +74,8 @@ void tlb_flush(CPUArchState *env, int flush_global) =20 memset(cpu->tb_jmp_cache, 0, TB_JMP_CACHE_SIZE * sizeof(void *)); =20 - env->tlb_flush_addr =3D -1; - env->tlb_flush_mask =3D 0; + cpu->tlb_flush_addr =3D -1; + cpu->tlb_flush_mask =3D 0; tlb_flush_count++; } =20 @@ -101,11 +101,11 @@ void tlb_flush_page(CPUArchState *env, target_ulong= addr) printf("tlb_flush_page: " TARGET_FMT_lx "\n", addr); #endif /* Check if we need to flush due to large pages. */ - if ((addr & env->tlb_flush_mask) =3D=3D env->tlb_flush_addr) { + if ((addr & cpu->tlb_flush_mask) =3D=3D cpu->tlb_flush_addr) { #if defined(DEBUG_TLB) - printf("tlb_flush_page: forced full flush (" - TARGET_FMT_lx "/" TARGET_FMT_lx ")\n", - env->tlb_flush_addr, env->tlb_flush_mask); + printf("tlb_flush_page: forced full flush (%" + VADDR_PRIx "/%" VADDR_PRIx ")\n", + cpu->tlb_flush_addr, cpu->tlb_flush_mask); #endif tlb_flush(env, 1); return; @@ -215,22 +215,23 @@ void tlb_set_dirty(CPUArchState *env, target_ulong = vaddr) static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr, target_ulong size) { + CPUState *cpu =3D ENV_GET_CPU(env); target_ulong mask =3D ~(size - 1); =20 - if (env->tlb_flush_addr =3D=3D (target_ulong)-1) { - env->tlb_flush_addr =3D vaddr & mask; - env->tlb_flush_mask =3D mask; + if ((target_ulong)cpu->tlb_flush_addr =3D=3D (target_ulong)-1) { + cpu->tlb_flush_addr =3D vaddr & mask; + cpu->tlb_flush_mask =3D mask; return; } /* Extend the existing region to include the new page. This is a compromise between unnecessary flushes and the cost of maintaining a full variable size TLB. */ - mask &=3D env->tlb_flush_mask; - while (((env->tlb_flush_addr ^ vaddr) & mask) !=3D 0) { + mask &=3D cpu->tlb_flush_mask; + while (((cpu->tlb_flush_addr ^ vaddr) & mask) !=3D 0) { mask <<=3D 1; } - env->tlb_flush_addr &=3D mask; - env->tlb_flush_mask =3D mask; + cpu->tlb_flush_addr &=3D mask; + cpu->tlb_flush_mask =3D mask; } =20 /* Add a new TLB entry. At most one entry for a given virtual address diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index d090594..460f7cf 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -103,8 +103,6 @@ QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) !=3D (1 << CPU_= TLB_ENTRY_BITS)); /* The meaning of the MMU modes is defined in the target code. */ = \ CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; = \ hwaddr iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ - target_ulong tlb_flush_addr; = \ - target_ulong tlb_flush_mask; =20 #else =20 diff --git a/include/qom/cpu.h b/include/qom/cpu.h index fc3d345..5349805 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -252,6 +252,9 @@ struct CPUState { =20 void *opaque; =20 + vaddr tlb_flush_addr; + vaddr tlb_flush_mask; + /* In order to avoid passing too many arguments to the MMIO helpers, * we store some rarely used information in the CPU context. */ --=20 1.8.1.4