From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47974) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VHAba-0000Ts-Sl for qemu-devel@nongnu.org; Wed, 04 Sep 2013 06:46:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VHAbU-0006R1-Tg for qemu-devel@nongnu.org; Wed, 04 Sep 2013 06:46:34 -0400 Received: from mx1.redhat.com ([209.132.183.28]:65053) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VHAbU-0006Qp-MM for qemu-devel@nongnu.org; Wed, 04 Sep 2013 06:46:28 -0400 Received: from int-mx11.intmail.prod.int.phx2.redhat.com (int-mx11.intmail.prod.int.phx2.redhat.com [10.5.11.24]) by mx1.redhat.com (8.14.4/8.14.4) with ESMTP id r84AkSmH032705 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK) for ; Wed, 4 Sep 2013 06:46:28 -0400 Date: Wed, 4 Sep 2013 13:48:29 +0300 From: "Michael S. Tsirkin" Message-ID: <1378291667-8516-2-git-send-email-mst@redhat.com> References: <1378291667-8516-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1378291667-8516-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PATCH 1/6] q35: make pci window address/size match guest cfg List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: imammedo@redhat.com For Q35, MMCFG address and size are guest configurable. Update w32 property to make it behave accordingly. Signed-off-by: Michael S. Tsirkin --- hw/pci-host/q35.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index 4febd24..3f1d447 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -214,6 +214,16 @@ static void mch_update_pciexbar(MCHPCIState *mch) } addr = pciexbar & addr_mask; pcie_host_mmcfg_update(pehb, enable, addr, length); + /* Leave enough space for the MCFG BAR */ + /* + * TODO: this matches current bios behaviour, but it's not a power of two, + * which means an MTRR can't cover it exactly. + */ + if (enable) { + mch->pci_info.w32.begin = addr + length; + } else { + mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; + } } /* PAM */ -- MST