From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51506) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VHKHA-0007Ir-BN for qemu-devel@nongnu.org; Wed, 04 Sep 2013 17:06:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VHKH3-0003bV-QS for qemu-devel@nongnu.org; Wed, 04 Sep 2013 17:06:08 -0400 Received: from mail-qc0-x22f.google.com ([2607:f8b0:400d:c01::22f]:55946) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VHKH3-0003bN-My for qemu-devel@nongnu.org; Wed, 04 Sep 2013 17:06:01 -0400 Received: by mail-qc0-f175.google.com with SMTP id v2so496689qcr.34 for ; Wed, 04 Sep 2013 14:06:01 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Wed, 4 Sep 2013 14:05:03 -0700 Message-Id: <1378328705-23006-15-git-send-email-rth@twiddle.net> In-Reply-To: <1378328705-23006-1-git-send-email-rth@twiddle.net> References: <1378328705-23006-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 14/16] tcg-i386: Remove "cb" output restriction from qemu_st8 for i386 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net Once we form a combined qemu_st_i32 opcode, we won't be able to have separate constraints based on size. This one is fairly easy to work around, since eax is available as a scratch register. When storing variable data, this tends to merely exchange one mov for another. E.g. -: mov %esi,%ecx ... -: mov %cl,(%edx) +: mov %esi,%eax +: mov %al,(%edx) Where we do have a regression is when storing constant data, in which we may load the constant into edi, when only ecx/ebx ought to be used. The proper way to recover this regression is to allow constants as arguments to qemu_st_i32, so that we never load the constant data into a register at all, must less the wrong register. TBD. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 89fe121..a3bf885 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -1503,6 +1503,12 @@ static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg datalo, TCGReg datahi, switch (memop & MO_SIZE) { case MO_8: + /* In 32-bit mode, 8-byte stores can only happen from [abcd]x. + Use the scratch register if necessary. */ + if (TCG_TARGET_REG_BITS == 32 && datalo >= 4) { + tcg_out_mov(s, TCG_TYPE_I32, scratch, datalo); + datalo = scratch; + } tcg_out_modrm_offset(s, OPC_MOVB_EvGv + P_REXB_R + seg, datalo, base, ofs); break; @@ -2108,7 +2114,7 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_qemu_ld32, { "r", "L" } }, { INDEX_op_qemu_ld64, { "r", "r", "L" } }, - { INDEX_op_qemu_st8, { "cb", "L" } }, + { INDEX_op_qemu_st8, { "L", "L" } }, { INDEX_op_qemu_st16, { "L", "L" } }, { INDEX_op_qemu_st32, { "L", "L" } }, { INDEX_op_qemu_st64, { "L", "L", "L" } }, @@ -2120,7 +2126,7 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_qemu_ld32, { "r", "L", "L" } }, { INDEX_op_qemu_ld64, { "r", "r", "L", "L" } }, - { INDEX_op_qemu_st8, { "cb", "L", "L" } }, + { INDEX_op_qemu_st8, { "L", "L", "L" } }, { INDEX_op_qemu_st16, { "L", "L", "L" } }, { INDEX_op_qemu_st32, { "L", "L", "L" } }, { INDEX_op_qemu_st64, { "L", "L", "L", "L" } }, -- 1.8.1.4