From: Richard Henderson <rth@twiddle.net>
To: qemu-devel@nongnu.org
Cc: aurelien@aurel32.net, Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 16/19] tcg-ia64: Move tlb addend load into tlb read
Date: Thu, 5 Sep 2013 23:50:38 -0700 [thread overview]
Message-ID: <1378450242-27080-17-git-send-email-rth@twiddle.net> (raw)
In-Reply-To: <1378450242-27080-1-git-send-email-rth@twiddle.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
---
tcg/ia64/tcg-target.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c
index 23be46c..819bca3 100644
--- a/tcg/ia64/tcg-target.c
+++ b/tcg/ia64/tcg-target.c
@@ -1569,7 +1569,7 @@ QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1])
> 0x1fffff)
/* Load and compare a TLB entry, and return the result in (p6, p7).
- R2 is loaded with the address of the addend TLB entry.
+ R2 is loaded with the addend TLB entry.
R57 is loaded with the address, zero extented on 32-bit targets.
R1, R3 are clobbered, leaving R56 free for...
BSWAP_1, BSWAP_2 and I-slot insns for swapping data for store. */
@@ -1625,7 +1625,7 @@ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGReg addr_reg,
TCG_REG_R2, off_add - off_rw),
bswap1);
tcg_out_bundle(s, mmI,
- INSN_NOP_M,
+ tcg_opc_m1 (TCG_REG_P0, OPC_LD8_M1, TCG_REG_R2, TCG_REG_R2),
tcg_opc_a6 (TCG_REG_P0, OPC_CMP_EQ_A6, TCG_REG_P6,
TCG_REG_P7, TCG_REG_R1, TCG_REG_R3),
bswap2);
@@ -1668,30 +1668,30 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args,
tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
(tcg_target_long) qemu_ld_helpers[s_bits]));
tcg_out_bundle(s, MmI,
- tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
+ tcg_opc_m3 (TCG_REG_P7, OPC_LD8_M3, TCG_REG_R3,
TCG_REG_R2, 8),
- tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
- TCG_REG_R3, TCG_REG_R57),
+ tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R2,
+ TCG_REG_R2, TCG_REG_R57),
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
TCG_REG_R3, 0));
if (bswap && s_bits == MO_16) {
tcg_out_bundle(s, MmI,
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
- TCG_REG_R8, TCG_REG_R3),
+ TCG_REG_R8, TCG_REG_R2),
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
TCG_REG_R8, TCG_REG_R8, 15, 15));
} else if (bswap && s_bits == MO_32) {
tcg_out_bundle(s, MmI,
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
- TCG_REG_R8, TCG_REG_R3),
+ TCG_REG_R8, TCG_REG_R2),
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12,
TCG_REG_R8, TCG_REG_R8, 31, 31));
} else {
tcg_out_bundle(s, mmI,
tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits],
- TCG_REG_R8, TCG_REG_R3),
+ TCG_REG_R8, TCG_REG_R2),
tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2),
INSN_NOP_I);
}
@@ -1763,10 +1763,10 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2,
(tcg_target_long) qemu_st_helpers[s_bits]));
tcg_out_bundle(s, MmI,
- tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3,
+ tcg_opc_m3 (TCG_REG_P7, OPC_LD8_M3, TCG_REG_R3,
TCG_REG_R2, 8),
- tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R3,
- TCG_REG_R3, TCG_REG_R57),
+ tcg_opc_a1 (TCG_REG_P6, OPC_ADD_A1, TCG_REG_R2,
+ TCG_REG_R2, TCG_REG_R57),
tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6,
TCG_REG_R3, 0));
tcg_out_bundle(s, mii,
@@ -1776,7 +1776,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args,
INSN_NOP_I);
tcg_out_bundle(s, miB,
tcg_opc_m4 (TCG_REG_P6, opc_st_m4[s_bits],
- store_reg, TCG_REG_R3),
+ store_reg, TCG_REG_R2),
tcg_opc_movi_a(TCG_REG_P7, TCG_REG_R59, mem_index),
tcg_opc_b5 (TCG_REG_P7, OPC_BR_CALL_SPTK_MANY_B5,
TCG_REG_B0, TCG_REG_B6));
--
1.8.3.1
next prev parent reply other threads:[~2013-09-06 6:51 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-06 6:50 [Qemu-devel] [PATCH 00/19] tcg-ia64 fixes and improvements Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 01/19] tcg-ia64: Use TCGMemOp within qemu_ldst routines Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 02/19] tcg-ia64: Use shortcuts for nop insns Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 03/19] tcg-ia64: Handle constant calls Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 04/19] tcg-ia64: Simplify brcond Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 05/19] tcg-ia64: Move AREG0 to R32 Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 06/19] tcg-ia64: Avoid unnecessary stop bit in tcg_out_alu Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 07/19] tcg-ia64: Use ADDS for small addition Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 08/19] tcg-ia64: Use SUB_A3 and ADDS_A4 for subtraction Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 09/19] tcg-ia64: Use A3 form of logical operations Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 10/19] tcg-ia64 Introduce tcg_opc_mov_a Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 11/19] tcg-ia64 Introduce tcg_opc_movi_a Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 12/19] tcg-ia64 Introduce tcg_opc_ext_i Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 13/19] tcg-ia64 Introduce tcg_opc_bswap64_i Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 14/19] tcg-ia64: Re-bundle the tlb load Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 15/19] tcg-ia64: Move bswap for store into " Richard Henderson
2013-09-06 6:50 ` Richard Henderson [this message]
2013-09-06 6:50 ` [Qemu-devel] [PATCH 17/19] tcg-i64: Reduce code duplication in tcg_out_qemu_ld Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 18/19] tcg-ia64: Convert to new ldst helpers Richard Henderson
2013-09-06 6:50 ` [Qemu-devel] [PATCH 19/19] tcg-ia64: Move part of softmmu slow path out of line Richard Henderson
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