From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32771) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VHpt6-0000s9-Kq for qemu-devel@nongnu.org; Fri, 06 Sep 2013 02:51:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VHpt0-00058M-OK for qemu-devel@nongnu.org; Fri, 06 Sep 2013 02:51:24 -0400 Received: from mail-qa0-x233.google.com ([2607:f8b0:400d:c00::233]:42705) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VHpt0-00058G-IE for qemu-devel@nongnu.org; Fri, 06 Sep 2013 02:51:18 -0400 Received: by mail-qa0-f51.google.com with SMTP id bv4so287797qab.10 for ; Thu, 05 Sep 2013 23:51:18 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Thu, 5 Sep 2013 23:50:23 -0700 Message-Id: <1378450242-27080-2-git-send-email-rth@twiddle.net> In-Reply-To: <1378450242-27080-1-git-send-email-rth@twiddle.net> References: <1378450242-27080-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH 01/19] tcg-ia64: Use TCGMemOp within qemu_ldst routines List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net, Richard Henderson Signed-off-by: Richard Henderson --- tcg/ia64/tcg-target.c | 171 ++++++++++++++++++++++++++------------------------ 1 file changed, 90 insertions(+), 81 deletions(-) diff --git a/tcg/ia64/tcg-target.c b/tcg/ia64/tcg-target.c index cd4f1ae..dcf4dd3 100644 --- a/tcg/ia64/tcg-target.c +++ b/tcg/ia64/tcg-target.c @@ -1494,7 +1494,7 @@ static inline void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGArg ret, R2 is loaded with the address of the addend TLB entry. R57 is loaded with the address, zero extented on 32-bit targets. */ static inline void tcg_out_qemu_tlb(TCGContext *s, TCGArg addr_reg, - int s_bits, uint64_t offset_rw, + TCGMemOp s_bits, uint64_t offset_rw, uint64_t offset_addend) { tcg_out_bundle(s, mII, @@ -1536,23 +1536,24 @@ static const void * const qemu_ld_helpers[4] = { helper_ldq_mmu, }; -static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) +static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, + TCGMemOp opc) { - int addr_reg, data_reg, mem_index, s_bits, bswap; - uint64_t opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 }; - uint64_t opc_ext_i29[8] = { OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0, - OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 }; + static const uint64_t opc_ld_m1[4] = { + OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 + }; + static const uint64_t opc_ext_i29[8] = { + OPC_ZXT1_I29, OPC_ZXT2_I29, OPC_ZXT4_I29, 0, + OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 + }; + int addr_reg, data_reg, mem_index; + TCGMemOp s_bits, bswap; data_reg = *args++; addr_reg = *args++; mem_index = *args; - s_bits = opc & 3; - -#ifdef TARGET_WORDS_BIGENDIAN - bswap = 1; -#else - bswap = 0; -#endif + s_bits = opc & MO_SIZE; + bswap = opc & MO_BSWAP; /* Read the TLB entry */ tcg_out_qemu_tlb(s, addr_reg, s_bits, @@ -1573,14 +1574,14 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) TCG_REG_R3, TCG_REG_R57), tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, TCG_REG_R3, 0)); - if (bswap && s_bits == 1) { + if (bswap && s_bits == MO_16) { tcg_out_bundle(s, MmI, tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], TCG_REG_R8, TCG_REG_R3), tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), tcg_opc_i12(TCG_REG_P6, OPC_DEP_Z_I12, TCG_REG_R8, TCG_REG_R8, 15, 15)); - } else if (bswap && s_bits == 2) { + } else if (bswap && s_bits == MO_32) { tcg_out_bundle(s, MmI, tcg_opc_m1 (TCG_REG_P6, opc_ld_m1[s_bits], TCG_REG_R8, TCG_REG_R3), @@ -1594,7 +1595,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); } - if (!bswap || s_bits == 0) { + if (!bswap) { tcg_out_bundle(s, miB, tcg_opc_a5 (TCG_REG_P7, OPC_ADDL_A5, TCG_REG_R58, mem_index, TCG_REG_R0), @@ -1611,7 +1612,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) TCG_REG_B0, TCG_REG_B6)); } - if (opc == 3) { + if (s_bits == MO_64) { tcg_out_bundle(s, miI, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), @@ -1621,7 +1622,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_out_bundle(s, miI, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), - tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc], + tcg_opc_i29(TCG_REG_P0, opc_ext_i29[opc & MO_SSIZE], data_reg, TCG_REG_R8)); } } @@ -1635,22 +1636,21 @@ static const void * const qemu_st_helpers[4] = { helper_stq_mmu, }; -static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) +static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, + TCGMemOp opc) { - int addr_reg, data_reg, mem_index, bswap; - uint64_t opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 }; + static const uint64_t opc_st_m4[4] = { + OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 + }; + int addr_reg, data_reg, mem_index; + TCGMemOp s_bits; data_reg = *args++; addr_reg = *args++; mem_index = *args; + s_bits = opc & MO_SIZE; -#ifdef TARGET_WORDS_BIGENDIAN - bswap = 1; -#else - bswap = 0; -#endif - - tcg_out_qemu_tlb(s, addr_reg, opc, + tcg_out_qemu_tlb(s, addr_reg, s_bits, offsetof(CPUArchState, tlb_table[mem_index][0].addr_write), offsetof(CPUArchState, tlb_table[mem_index][0].addend)); @@ -1658,9 +1658,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_out_bundle(s, mLX, tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R56, 0, TCG_AREG0), - tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[opc]), + tcg_opc_l2 ((tcg_target_long) qemu_st_helpers[s_bits]), tcg_opc_x2 (TCG_REG_P7, OPC_MOVL_X2, TCG_REG_R2, - (tcg_target_long) qemu_st_helpers[opc])); + (tcg_target_long) qemu_st_helpers[s_bits])); tcg_out_bundle(s, MmI, tcg_opc_m3 (TCG_REG_P0, OPC_LD8_M3, TCG_REG_R3, TCG_REG_R2, 8), @@ -1669,14 +1669,20 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i21(TCG_REG_P7, OPC_MOV_I21, TCG_REG_B6, TCG_REG_R3, 0)); - if (!bswap || opc == 0) { + switch (opc) { + case MO_8: + case MO_16: + case MO_32: + case MO_64: tcg_out_bundle(s, mii, tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), tcg_opc_a4 (TCG_REG_P7, OPC_ADDS_A4, TCG_REG_R58, 0, data_reg), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); - } else if (opc == 1) { + break; + + case MO_16 | MO_BSWAP: tcg_out_bundle(s, miI, tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), @@ -1690,7 +1696,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, TCG_REG_R2, TCG_REG_R2, 0xb)); data_reg = TCG_REG_R2; - } else if (opc == 2) { + break; + + case MO_32 | MO_BSWAP: tcg_out_bundle(s, miI, tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), @@ -1704,7 +1712,9 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, TCG_REG_R2, TCG_REG_R2, 0xb)); data_reg = TCG_REG_R2; - } else if (opc == 3) { + break; + + case MO_64 | MO_BSWAP: tcg_out_bundle(s, miI, tcg_opc_m1 (TCG_REG_P7, OPC_LD8_M1, TCG_REG_R1, TCG_REG_R2), @@ -1713,6 +1723,10 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i3 (TCG_REG_P6, OPC_MUX1_I3, TCG_REG_R2, data_reg, 0xb)); data_reg = TCG_REG_R2; + break; + + default: + tcg_abort(); } tcg_out_bundle(s, miB, @@ -1726,7 +1740,8 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) #else /* !CONFIG_SOFTMMU */ -static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) +static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, + TCGMemOp opc) { static uint64_t const opc_ld_m1[4] = { OPC_LD1_M1, OPC_LD2_M1, OPC_LD4_M1, OPC_LD8_M1 @@ -1734,17 +1749,13 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) static uint64_t const opc_sxt_i29[4] = { OPC_SXT1_I29, OPC_SXT2_I29, OPC_SXT4_I29, 0 }; - int addr_reg, data_reg, s_bits, bswap; + int addr_reg, data_reg; + TCGMemOp s_bits, bswap; data_reg = *args++; addr_reg = *args++; - s_bits = opc & 3; - -#ifdef TARGET_WORDS_BIGENDIAN - bswap = 1; -#else - bswap = 0; -#endif + s_bits = opc & MO_SIZE; + bswap = opc & MO_BSWAP; #if TARGET_LONG_BITS == 32 if (GUEST_BASE != 0) { @@ -1762,8 +1773,8 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); } - if (!bswap || s_bits == 0) { - if (s_bits == opc) { + if (!bswap) { + if (!(opc & MO_SIGN)) { tcg_out_bundle(s, miI, tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], data_reg, TCG_REG_R2), @@ -1777,7 +1788,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i29(TCG_REG_P0, opc_sxt_i29[s_bits], data_reg, data_reg)); } - } else if (s_bits == 3) { + } else if (s_bits == MO_64) { tcg_out_bundle(s, mII, tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], data_reg, TCG_REG_R2), @@ -1785,7 +1796,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, data_reg, data_reg, 0xb)); } else { - if (s_bits == 1) { + if (s_bits == MO_16) { tcg_out_bundle(s, mII, tcg_opc_m1 (TCG_REG_P0, opc_ld_m1[s_bits], data_reg, TCG_REG_R2), @@ -1800,7 +1811,7 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, data_reg, data_reg, 31, 31)); } - if (opc == s_bits) { + if (!(opc & MO_SIGN)) { tcg_out_bundle(s, miI, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), @@ -1831,28 +1842,28 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); } - if (bswap && s_bits == 1) { + if (bswap && s_bits == MO_16) { tcg_out_bundle(s, mII, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, data_reg, data_reg, 15, 15), tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, data_reg, data_reg, 0xb)); - } else if (bswap && s_bits == 2) { + } else if (bswap && s_bits == MO_32) { tcg_out_bundle(s, mII, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, data_reg, data_reg, 31, 31), tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, data_reg, data_reg, 0xb)); - } else if (bswap && s_bits == 3) { + } else if (bswap && s_bits == MO_64) { tcg_out_bundle(s, miI, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, data_reg, data_reg, 0xb)); } - if (s_bits != opc) { + if (opc & MO_SIGN) { tcg_out_bundle(s, miI, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), @@ -1862,24 +1873,22 @@ static inline void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int opc) #endif } -static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) +static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, + TCGMemOp opc) { static uint64_t const opc_st_m4[4] = { OPC_ST1_M4, OPC_ST2_M4, OPC_ST4_M4, OPC_ST8_M4 }; - int addr_reg, data_reg, bswap; + int addr_reg, data_reg; #if TARGET_LONG_BITS == 64 uint64_t add_guest_base; #endif + TCGMemOp s_bits, bswap; data_reg = *args++; addr_reg = *args++; - -#ifdef TARGET_WORDS_BIGENDIAN - bswap = 1; -#else - bswap = 0; -#endif + s_bits = opc & MO_SIZE; + bswap = opc & MO_BSWAP; #if TARGET_LONG_BITS == 32 if (GUEST_BASE != 0) { @@ -1898,7 +1907,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) } if (bswap) { - if (opc == 1) { + if (s_bits == MO_16) { tcg_out_bundle(s, mII, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, @@ -1906,7 +1915,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, TCG_REG_R3, TCG_REG_R3, 0xb)); data_reg = TCG_REG_R3; - } else if (opc == 2) { + } else if (s_bits == MO_32) { tcg_out_bundle(s, mII, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, @@ -1914,7 +1923,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, TCG_REG_R3, TCG_REG_R3, 0xb)); data_reg = TCG_REG_R3; - } else if (opc == 3) { + } else if (s_bits == MO_64) { tcg_out_bundle(s, miI, tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), @@ -1924,7 +1933,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) } } tcg_out_bundle(s, mmI, - tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], + tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], data_reg, TCG_REG_R2), tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); @@ -1937,14 +1946,14 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) add_guest_base = tcg_opc_m48(TCG_REG_P0, OPC_NOP_M48, 0); } - if (!bswap || opc == 0) { + if (!bswap) { tcg_out_bundle(s, (GUEST_BASE ? MmI : mmI), add_guest_base, - tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], + tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], data_reg, addr_reg), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); } else { - if (opc == 1) { + if (s_bits == MO_16) { tcg_out_bundle(s, mII, add_guest_base, tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, @@ -1952,7 +1961,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, TCG_REG_R3, TCG_REG_R3, 0xb)); data_reg = TCG_REG_R3; - } else if (opc == 2) { + } else if (s_bits == MO_32) { tcg_out_bundle(s, mII, add_guest_base, tcg_opc_i12(TCG_REG_P0, OPC_DEP_Z_I12, @@ -1960,7 +1969,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) tcg_opc_i3 (TCG_REG_P0, OPC_MUX1_I3, TCG_REG_R3, TCG_REG_R3, 0xb)); data_reg = TCG_REG_R3; - } else if (opc == 3) { + } else if (s_bits == MO_64) { tcg_out_bundle(s, miI, add_guest_base, tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), @@ -1969,7 +1978,7 @@ static inline void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) data_reg = TCG_REG_R3; } tcg_out_bundle(s, miI, - tcg_opc_m4 (TCG_REG_P0, opc_st_m4[opc], + tcg_opc_m4 (TCG_REG_P0, opc_st_m4[s_bits], data_reg, addr_reg), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0), tcg_opc_i18(TCG_REG_P0, OPC_NOP_I18, 0)); @@ -2201,39 +2210,39 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, break; case INDEX_op_qemu_ld8u: - tcg_out_qemu_ld(s, args, 0); + tcg_out_qemu_ld(s, args, MO_UB); break; case INDEX_op_qemu_ld8s: - tcg_out_qemu_ld(s, args, 0 | 4); + tcg_out_qemu_ld(s, args, MO_SB); break; case INDEX_op_qemu_ld16u: - tcg_out_qemu_ld(s, args, 1); + tcg_out_qemu_ld(s, args, MO_TEUW); break; case INDEX_op_qemu_ld16s: - tcg_out_qemu_ld(s, args, 1 | 4); + tcg_out_qemu_ld(s, args, MO_TESW); break; case INDEX_op_qemu_ld32: case INDEX_op_qemu_ld32u: - tcg_out_qemu_ld(s, args, 2); + tcg_out_qemu_ld(s, args, MO_TEUL); break; case INDEX_op_qemu_ld32s: - tcg_out_qemu_ld(s, args, 2 | 4); + tcg_out_qemu_ld(s, args, MO_TESL); break; case INDEX_op_qemu_ld64: - tcg_out_qemu_ld(s, args, 3); + tcg_out_qemu_ld(s, args, MO_TEQ); break; case INDEX_op_qemu_st8: - tcg_out_qemu_st(s, args, 0); + tcg_out_qemu_st(s, args, MO_UB); break; case INDEX_op_qemu_st16: - tcg_out_qemu_st(s, args, 1); + tcg_out_qemu_st(s, args, MO_TEUW); break; case INDEX_op_qemu_st32: - tcg_out_qemu_st(s, args, 2); + tcg_out_qemu_st(s, args, MO_TEUL); break; case INDEX_op_qemu_st64: - tcg_out_qemu_st(s, args, 3); + tcg_out_qemu_st(s, args, MO_TEQ); break; default: -- 1.8.3.1