From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:57042) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VIzO0-0001h4-Ml for qemu-devel@nongnu.org; Mon, 09 Sep 2013 07:12:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VIzNt-0004Nh-UA for qemu-devel@nongnu.org; Mon, 09 Sep 2013 07:12:04 -0400 Received: from mx1.redhat.com ([209.132.183.28]:19079) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VIzNt-0004Na-MN for qemu-devel@nongnu.org; Mon, 09 Sep 2013 07:11:57 -0400 From: Marcel Apfelbaum Date: Mon, 9 Sep 2013 14:11:54 +0300 Message-Id: <1378725114-13197-3-git-send-email-marcel.a@redhat.com> In-Reply-To: <1378725114-13197-1-git-send-email-marcel.a@redhat.com> References: <1378725114-13197-1-git-send-email-marcel.a@redhat.com> Subject: [Qemu-devel] [PATCH RFC v2 2/2] hw/pci: handle unassigned pci addresses List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, pbonzini@redhat.com, aliguori@us.ibm.com, jan.kiszka@siemens.com, mst@redhat.com Created a MemoryRegion with negative priority that spans over all the pci address space. It "intercepts" the accesses to unassigned pci address space and will follow the pci spec: 1. returns -1 on read 2. does nothing on write 3. sets the RECEIVED MASTER ABORT bit in the STATUS register of the device that initiated the transaction Note: This implementation assumes that all the reads/writes to the pci address space are done by the cpu. Signed-off-by: Marcel Apfelbaum --- Changes from v1: - "pci-unassigned-mem" MemoryRegion resides now in PCIBus and not on various Host Bridges - "pci-unassgined-mem" does not have a ".valid.accept" field and implements read write methods hw/pci/pci.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ include/hw/pci/pci_bus.h | 1 + 2 files changed, 47 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index d00682e..b6a8026 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -283,6 +283,43 @@ const char *pci_root_bus_path(PCIDevice *dev) return rootbus->qbus.name; } +static void unassigned_mem_access(PCIBus *bus) +{ + /* FIXME assumption: memory access to the pci address + * space is always initiated by the host bridge + * (device 0 on the bus) */ + PCIDevice *d = bus->devices[0]; + if (!d) { + return; + } + + pci_word_test_and_set_mask(d->config + PCI_STATUS, + PCI_STATUS_REC_MASTER_ABORT); +} + +static uint64_t unassigned_mem_read(void *opaque, hwaddr addr, unsigned size) +{ + PCIBus *bus = opaque; + unassigned_mem_access(bus); + + return -1ULL; +} + +static void unassigned_mem_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) +{ + PCIBus *bus = opaque; + unassigned_mem_access(bus); +} + +static const MemoryRegionOps unassigned_mem_ops = { + .read = unassigned_mem_read, + .write = unassigned_mem_write, + .endianness = DEVICE_NATIVE_ENDIAN, +}; + +#define UNASSIGNED_MEM_PRIORITY -1 + static void pci_bus_init(PCIBus *bus, DeviceState *parent, const char *name, MemoryRegion *address_space_mem, @@ -294,6 +331,15 @@ static void pci_bus_init(PCIBus *bus, DeviceState *parent, bus->address_space_mem = address_space_mem; bus->address_space_io = address_space_io; + + memory_region_init_io(&bus->unassigned_mem, OBJECT(bus), + &unassigned_mem_ops, bus, "pci-unassigned", + memory_region_size(bus->address_space_mem)); + memory_region_add_subregion_overlap(bus->address_space_mem, + bus->address_space_mem->addr, + &bus->unassigned_mem, + UNASSIGNED_MEM_PRIORITY); + /* host bridge */ QLIST_INIT(&bus->child); diff --git a/include/hw/pci/pci_bus.h b/include/hw/pci/pci_bus.h index 9df1788..4cc25a3 100644 --- a/include/hw/pci/pci_bus.h +++ b/include/hw/pci/pci_bus.h @@ -23,6 +23,7 @@ struct PCIBus { PCIDevice *parent_dev; MemoryRegion *address_space_mem; MemoryRegion *address_space_io; + MemoryRegion unassigned_mem; QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */ QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */ -- 1.8.3.1