From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34708) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJ5G1-0004vb-8W for qemu-devel@nongnu.org; Mon, 09 Sep 2013 13:28:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VJ5Fu-0008TT-NF for qemu-devel@nongnu.org; Mon, 09 Sep 2013 13:28:13 -0400 Received: from hall.aurel32.net ([2001:470:1f0b:4a8::1]:38650) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJ5Fu-0008TJ-Fl for qemu-devel@nongnu.org; Mon, 09 Sep 2013 13:28:06 -0400 From: Aurelien Jarno Date: Mon, 9 Sep 2013 19:27:50 +0200 Message-Id: <1378747670-25512-5-git-send-email-aurelien@aurel32.net> In-Reply-To: <1378747670-25512-1-git-send-email-aurelien@aurel32.net> References: <1378747670-25512-1-git-send-email-aurelien@aurel32.net> Subject: [Qemu-devel] [PATCH v2 4/4] tcg/optimize: add known-zero bits compute for load ops List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Aurelien Jarno , Richard Henderson Cc: Richard Henderson Cc: Paolo Bonzini Signed-off-by: Aurelien Jarno --- tcg/optimize.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/tcg/optimize.c b/tcg/optimize.c index b1f736b..044f456 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -787,6 +787,19 @@ static TCGArg *tcg_constant_folding(TCGContext *s, uint16_t *tcg_opc_ptr, mask = temps[args[3]].mask | temps[args[4]].mask; break; + CASE_OP_32_64(ld8u): + case INDEX_op_qemu_ld8u: + mask = 0xff; + break; + CASE_OP_32_64(ld16u): + case INDEX_op_qemu_ld16u: + mask = 0xffff; + break; + case INDEX_op_ld32u_i64: + case INDEX_op_qemu_ld32u: + mask = 0xffffffffu; + break; + default: break; } -- 1.7.10.4