From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51669) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJT37-0004cI-RN for qemu-devel@nongnu.org; Tue, 10 Sep 2013 14:52:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VJT36-0005Ev-ED for qemu-devel@nongnu.org; Tue, 10 Sep 2013 14:52:29 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:43712 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJT36-0005Dk-81 for qemu-devel@nongnu.org; Tue, 10 Sep 2013 14:52:28 -0400 From: Peter Maydell Date: Tue, 10 Sep 2013 19:52:04 +0100 Message-Id: <1378839142-7726-11-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1378839142-7726-1-git-send-email-peter.maydell@linaro.org> References: <1378839142-7726-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 10/28] target-arm: Export cpu_env List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org From: Alexander Graf The cpu_env tcg variable will be used by both the AArch32 and AArch64 handling code. Unstaticify it, so that both sides can make use of it. Signed-off-by: Alexander Graf Signed-off-by: John Rigby Signed-off-by: Peter Maydell Message-id: 1378235544-22290-5-git-send-email-peter.maydell@linaro.org Message-id: 1368505980-17151-3-git-send-email-john.rigby@linaro.org Signed-off-by: Peter Maydell --- target-arm/translate.c | 2 +- target-arm/translate.h | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index 450a0b6..2605833 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -61,7 +61,7 @@ static uint32_t gen_opc_condexec_bits[OPC_BUF_SIZE]; #define DISAS_WFI 4 #define DISAS_SWI 5 -static TCGv_ptr cpu_env; +TCGv_ptr cpu_env; /* We reuse the same 64-bit temporaries for efficiency. */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; static TCGv_i32 cpu_R[16]; diff --git a/target-arm/translate.h b/target-arm/translate.h index e727bc6..8ba1433 100644 --- a/target-arm/translate.h +++ b/target-arm/translate.h @@ -24,4 +24,6 @@ typedef struct DisasContext { int vec_stride; } DisasContext; +extern TCGv_ptr cpu_env; + #endif /* TARGET_ARM_TRANSLATE_H */ -- 1.7.9.5