From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51843) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJT3C-0004lo-Qh for qemu-devel@nongnu.org; Tue, 10 Sep 2013 14:52:36 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VJT39-0005Nm-Jp for qemu-devel@nongnu.org; Tue, 10 Sep 2013 14:52:34 -0400 Received: from 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.d.1.0.0.b.8.0.1.0.0.2.ip6.arpa ([2001:8b0:1d0::1]:43707 helo=mnementh.archaic.org.uk) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VJT39-00056X-8f for qemu-devel@nongnu.org; Tue, 10 Sep 2013 14:52:31 -0400 From: Peter Maydell Date: Tue, 10 Sep 2013 19:52:06 +0100 Message-Id: <1378839142-7726-13-git-send-email-peter.maydell@linaro.org> In-Reply-To: <1378839142-7726-1-git-send-email-peter.maydell@linaro.org> References: <1378839142-7726-1-git-send-email-peter.maydell@linaro.org> Subject: [Qemu-devel] [PULL 12/28] target-arm: Pass DisasContext* to gen_set_pc_im() List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Anthony Liguori Cc: qemu-devel@nongnu.org We want gen_set_pc_im() to work for both AArch64 and AArch32, but to do this we'll need the DisasContext* so we can tell which mode we're in, so pass it in as a parameter. Signed-off-by: Peter Maydell Message-id: 1378235544-22290-7-git-send-email-peter.maydell@linaro.org --- target-arm/translate.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target-arm/translate.c b/target-arm/translate.c index ca411b3..2d8e0a5 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -905,7 +905,7 @@ DO_GEN_ST(st8) DO_GEN_ST(st16) DO_GEN_ST(st32) -static inline void gen_set_pc_im(target_ulong val) +static inline void gen_set_pc_im(DisasContext *s, target_ulong val) { tcg_gen_movi_i32(cpu_R[15], val); } @@ -3420,10 +3420,10 @@ static inline void gen_goto_tb(DisasContext *s, int n, target_ulong dest) tb = s->tb; if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) { tcg_gen_goto_tb(n); - gen_set_pc_im(dest); + gen_set_pc_im(s, dest); tcg_gen_exit_tb((uintptr_t)tb + n); } else { - gen_set_pc_im(dest); + gen_set_pc_im(s, dest); tcg_gen_exit_tb(0); } } @@ -3552,7 +3552,7 @@ gen_set_condexec (DisasContext *s) static void gen_exception_insn(DisasContext *s, int offset, int excp) { gen_set_condexec(s); - gen_set_pc_im(s->pc - offset); + gen_set_pc_im(s, s->pc - offset); gen_exception(excp); s->is_jmp = DISAS_JUMP; } @@ -3561,7 +3561,7 @@ static void gen_nop_hint(DisasContext *s, int val) { switch (val) { case 3: /* wfi */ - gen_set_pc_im(s->pc); + gen_set_pc_im(s, s->pc); s->is_jmp = DISAS_WFI; break; case 2: /* wfe */ @@ -6338,7 +6338,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) if (isread) { return 1; } - gen_set_pc_im(s->pc); + gen_set_pc_im(s, s->pc); s->is_jmp = DISAS_WFI; return 0; default: @@ -6358,7 +6358,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tmp64 = tcg_const_i64(ri->resetvalue); } else if (ri->readfn) { TCGv_ptr tmpptr; - gen_set_pc_im(s->pc); + gen_set_pc_im(s, s->pc); tmp64 = tcg_temp_new_i64(); tmpptr = tcg_const_ptr(ri); gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr); @@ -6381,7 +6381,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tmp = tcg_const_i32(ri->resetvalue); } else if (ri->readfn) { TCGv_ptr tmpptr; - gen_set_pc_im(s->pc); + gen_set_pc_im(s, s->pc); tmp = tcg_temp_new_i32(); tmpptr = tcg_const_ptr(ri); gen_helper_get_cp_reg(tmp, cpu_env, tmpptr); @@ -6416,7 +6416,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) tcg_temp_free_i32(tmphi); if (ri->writefn) { TCGv_ptr tmpptr = tcg_const_ptr(ri); - gen_set_pc_im(s->pc); + gen_set_pc_im(s, s->pc); gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64); tcg_temp_free_ptr(tmpptr); } else { @@ -6427,7 +6427,7 @@ static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn) if (ri->writefn) { TCGv_i32 tmp; TCGv_ptr tmpptr; - gen_set_pc_im(s->pc); + gen_set_pc_im(s, s->pc); tmp = load_reg(s, rt); tmpptr = tcg_const_ptr(ri); gen_helper_set_cp_reg(cpu_env, tmpptr, tmp); @@ -8036,7 +8036,7 @@ static void disas_arm_insn(CPUARMState * env, DisasContext *s) break; case 0xf: /* swi */ - gen_set_pc_im(s->pc); + gen_set_pc_im(s, s->pc); s->is_jmp = DISAS_SWI; break; default: @@ -9940,7 +9940,7 @@ static void disas_thumb_insn(CPUARMState *env, DisasContext *s) if (cond == 0xf) { /* swi */ - gen_set_pc_im(s->pc); + gen_set_pc_im(s, s->pc); s->is_jmp = DISAS_SWI; break; } @@ -10190,7 +10190,7 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, gen_set_label(dc->condlabel); } if (dc->condjmp || !dc->is_jmp) { - gen_set_pc_im(dc->pc); + gen_set_pc_im(dc, dc->pc); dc->condjmp = 0; } gen_set_condexec(dc); -- 1.7.9.5