From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36525) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKCKV-0007Qe-5D for qemu-devel@nongnu.org; Thu, 12 Sep 2013 15:13:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VKCKP-0002wl-3W for qemu-devel@nongnu.org; Thu, 12 Sep 2013 15:13:27 -0400 From: Stefan Weil Date: Thu, 12 Sep 2013 21:13:11 +0200 Message-Id: <1379013193-20691-2-git-send-email-sw@weilnetz.de> In-Reply-To: <1379013193-20691-1-git-send-email-sw@weilnetz.de> References: <1379013193-20691-1-git-send-email-sw@weilnetz.de> Subject: [Qemu-devel] [PATCH 1/3] tci: Add implementation of rotl_i64, rotr_i64 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel Cc: Peter Maydell , Stefan Weil , qemu-stable , Richard Henderson It is used by qemu-ppc64 when running Debian's busybox-static. Cc: qemu-stable Signed-off-by: Stefan Weil Reviewed-by: Richard Henderson --- tcg/tci/tcg-target.c | 1 - tci.c | 10 +++++++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/tcg/tci/tcg-target.c b/tcg/tci/tcg-target.c index 233ab3b..4976bec 100644 --- a/tcg/tci/tcg-target.c +++ b/tcg/tci/tcg-target.c @@ -670,7 +670,6 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, case INDEX_op_shl_i64: case INDEX_op_shr_i64: case INDEX_op_sar_i64: - /* TODO: Implementation of rotl_i64, rotr_i64 missing in tci.c. */ case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */ tcg_out_r(s, args[0]); diff --git a/tci.c b/tci.c index 18c888e..94b7851 100644 --- a/tci.c +++ b/tci.c @@ -952,8 +952,16 @@ uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr) break; #if TCG_TARGET_HAS_rot_i64 case INDEX_op_rotl_i64: + t0 = *tb_ptr++; + t1 = tci_read_ri64(&tb_ptr); + t2 = tci_read_ri64(&tb_ptr); + tci_write_reg64(t0, (t1 << t2) | (t1 >> (64 - t2))); + break; case INDEX_op_rotr_i64: - TODO(); + t0 = *tb_ptr++; + t1 = tci_read_ri64(&tb_ptr); + t2 = tci_read_ri64(&tb_ptr); + tci_write_reg64(t0, (t1 >> t2) | (t1 << (64 - t2))); break; #endif #if TCG_TARGET_HAS_deposit_i64 -- 1.7.10.4