From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34607) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxoH-0001Px-K1 for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VKxoB-00045q-Na for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:21 -0400 Received: from mail-pb0-x231.google.com ([2607:f8b0:400e:c01::231]:54219) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxoB-000457-BD for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:15 -0400 Received: by mail-pb0-f49.google.com with SMTP id xb4so2602688pbc.22 for ; Sat, 14 Sep 2013 14:55:14 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sat, 14 Sep 2013 14:54:30 -0700 Message-Id: <1379195690-6509-14-git-send-email-rth@twiddle.net> In-Reply-To: <1379195690-6509-1-git-send-email-rth@twiddle.net> References: <1379195690-6509-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v4 13/33] tcg-aarch64: Support andc, orc, eqv, not List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, claudio.fontana@gmail.com Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 65 ++++++++++++++++++++++++++++++++++++++++++------ tcg/aarch64/tcg-target.h | 16 ++++++------ 2 files changed, 65 insertions(+), 16 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index bc651ac..5b4eeee 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -258,10 +258,12 @@ typedef enum { INSN_EORI = 0x52000000, /* Logical shifted register instructions */ - INSN_AND = 0x0a000000, - INSN_ORR = 0x2a000000, - INSN_EOR = 0x4a000000, - INSN_ANDS = 0x6a000000, + INSN_AND = 0x0a000000, + INSN_BIC = 0x0a200000, + INSN_ORR = 0x2a000000, + INSN_ORN = 0x2a200000, + INSN_EOR = 0x4a000000, + INSN_EON = 0x4a200000, /* Add/subtract immediate instructions */ INSN_ADDI = 0x11000000, @@ -270,10 +272,10 @@ typedef enum { INSN_SUBSI = 0x71000000, /* Add/subtract shifted register instructions */ - INSN_ADD = 0x0b000000, - INSN_ADDS = 0x2b000000, - INSN_SUB = 0x4b000000, - INSN_SUBS = 0x6b000000, + INSN_ADD = 0x0b000000, + INSN_ADDS = 0x2b000000, + INSN_SUB = 0x4b000000, + INSN_SUBS = 0x6b000000, /* Data-processing (2 source) instructions */ INSN_LSLV = 0x1ac02000, @@ -1270,6 +1272,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_andc_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_andc_i64: + if (c2) { + tcg_fmt_Rdn_limm(s, INSN_ANDI, ext, a0, a1, ~a2); + } else { + tcg_fmt_Rdnm(s, INSN_BIC, ext, a0, a1, a2); + } + break; + case INDEX_op_or_i32: a2 = (int32_t)a2; /* FALLTHRU */ @@ -1281,6 +1294,17 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_orc_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_orc_i64: + if (c2) { + tcg_fmt_Rdn_limm(s, INSN_ORRI, ext, a0, a1, ~a2); + } else { + tcg_fmt_Rdnm(s, INSN_ORN, ext, a0, a1, a2); + } + break; + case INDEX_op_xor_i32: a2 = (int32_t)a2; /* FALLTHRU */ @@ -1292,6 +1316,22 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, } break; + case INDEX_op_eqv_i32: + a2 = (int32_t)a2; + /* FALLTHRU */ + case INDEX_op_eqv_i64: + if (c2) { + tcg_fmt_Rdn_limm(s, INSN_EORI, ext, a0, a1, ~a2); + } else { + tcg_fmt_Rdnm(s, INSN_EON, ext, a0, a1, a2); + } + break; + + case INDEX_op_not_i64: + case INDEX_op_not_i32: + tcg_fmt_Rdnm(s, INSN_ORN, ext, a0, TCG_REG_XZR, a1); + break; + case INDEX_op_mul_i64: case INDEX_op_mul_i32: tcg_out_mul(s, ext, a0, a1, a2); @@ -1488,6 +1528,15 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_or_i64, { "r", "r", "rL" } }, { INDEX_op_xor_i32, { "r", "r", "rwL" } }, { INDEX_op_xor_i64, { "r", "r", "rL" } }, + { INDEX_op_andc_i32, { "r", "r", "rwL" } }, + { INDEX_op_andc_i64, { "r", "r", "rL" } }, + { INDEX_op_orc_i32, { "r", "r", "rwL" } }, + { INDEX_op_orc_i64, { "r", "r", "rL" } }, + { INDEX_op_eqv_i32, { "r", "r", "rwL" } }, + { INDEX_op_eqv_i64, { "r", "r", "rL" } }, + + { INDEX_op_not_i32, { "r", "r" } }, + { INDEX_op_not_i64, { "r", "r" } }, { INDEX_op_shl_i32, { "r", "r", "ri" } }, { INDEX_op_shr_i32, { "r", "r", "ri" } }, diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h index d3a1bc2..efc506b 100644 --- a/tcg/aarch64/tcg-target.h +++ b/tcg/aarch64/tcg-target.h @@ -47,12 +47,12 @@ typedef enum { #define TCG_TARGET_HAS_ext16u_i32 1 #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 -#define TCG_TARGET_HAS_not_i32 0 +#define TCG_TARGET_HAS_not_i32 1 #define TCG_TARGET_HAS_neg_i32 0 #define TCG_TARGET_HAS_rot_i32 1 -#define TCG_TARGET_HAS_andc_i32 0 -#define TCG_TARGET_HAS_orc_i32 0 -#define TCG_TARGET_HAS_eqv_i32 0 +#define TCG_TARGET_HAS_andc_i32 1 +#define TCG_TARGET_HAS_orc_i32 1 +#define TCG_TARGET_HAS_eqv_i32 1 #define TCG_TARGET_HAS_nand_i32 0 #define TCG_TARGET_HAS_nor_i32 0 #define TCG_TARGET_HAS_deposit_i32 0 @@ -75,12 +75,12 @@ typedef enum { #define TCG_TARGET_HAS_bswap16_i64 1 #define TCG_TARGET_HAS_bswap32_i64 1 #define TCG_TARGET_HAS_bswap64_i64 1 -#define TCG_TARGET_HAS_not_i64 0 +#define TCG_TARGET_HAS_not_i64 1 #define TCG_TARGET_HAS_neg_i64 0 #define TCG_TARGET_HAS_rot_i64 1 -#define TCG_TARGET_HAS_andc_i64 0 -#define TCG_TARGET_HAS_orc_i64 0 -#define TCG_TARGET_HAS_eqv_i64 0 +#define TCG_TARGET_HAS_andc_i64 1 +#define TCG_TARGET_HAS_orc_i64 1 +#define TCG_TARGET_HAS_eqv_i64 1 #define TCG_TARGET_HAS_nand_i64 0 #define TCG_TARGET_HAS_nor_i64 0 #define TCG_TARGET_HAS_deposit_i64 0 -- 1.8.3.1