[Qemu-devel] [PATCH v4 15/33] tcg-aarch64: Support movcond

[Richard Henderson <rth@twiddle.net>]

Signed-off-by: Richard Henderson <rth@twiddle.net>
---
 tcg/aarch64/tcg-target.c | 24 +++++++++++++++++++++++-
 tcg/aarch64/tcg-target.h |  4 ++--
 2 files changed, 25 insertions(+), 3 deletions(-)

diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 08a0cc4..e9a0f9b 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -289,6 +289,10 @@ typedef enum {
     INSN_LSRV  = 0x1ac02400,
     INSN_ASRV  = 0x1ac02800,
     INSN_RORV  = 0x1ac02c00,
+
+    /* Conditional select instructions */
+    INSN_CSEL  = 0x1a800000,
+    INSN_CSINC = 0x1a800400,
 } AArch64Insn;
 
 static inline enum aarch64_ldst_op_data
@@ -451,6 +455,14 @@ static void tcg_fmt_Rdn_limm(TCGContext *s, AArch64Insn insn, TCGType sf,
     tcg_fmt_Rdn_nrs(s, insn, sf, rd, rn, sf, r, c);
 }
 
+static inline void tcg_fmt_Rdnm_cond(TCGContext *s, AArch64Insn insn,
+                                     TCGType sf, TCGReg rd, TCGReg rn,
+                                     TCGReg rm, TCGCond c)
+{
+    tcg_out32(s, insn | sf << 31 | rm << 16 | rn << 5 | rd
+              | tcg_cond_to_aarch64[c] << 12);
+}
+
 static inline void tcg_out_ldst_9(TCGContext *s,
                                   enum aarch64_ldst_op_data op_data,
                                   enum aarch64_ldst_op_type op_type,
@@ -1414,7 +1426,15 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
         /* FALLTHRU */
     case INDEX_op_setcond_i64:
         tcg_out_cmp(s, ext, a1, a2, c2);
-        tcg_out_cset(s, 0, a0, args[3]);
+        tcg_out_cset(s, ext, a0, args[3]);
+        break;
+
+    case INDEX_op_movcond_i32:
+        a2 = (int32_t)a2;
+        /* FALLTHRU */
+    case INDEX_op_movcond_i64:
+        tcg_out_cmp(s, ext, a1, a2, c2);
+        tcg_fmt_Rdnm_cond(s, INSN_CSEL, ext, a0, REG0(3), REG0(4), args[5]);
         break;
 
     case INDEX_op_qemu_ld8u:
@@ -1573,6 +1593,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
     { INDEX_op_brcond_i64, { "r", "rA" } },
     { INDEX_op_setcond_i32, { "r", "r", "rwA" } },
     { INDEX_op_setcond_i64, { "r", "r", "rA" } },
+    { INDEX_op_movcond_i32, { "r", "r", "rwA", "rZ", "rZ" } },
+    { INDEX_op_movcond_i64, { "r", "r", "rwA", "rZ", "rZ" } },
 
     { INDEX_op_qemu_ld8u, { "r", "l" } },
     { INDEX_op_qemu_ld8s, { "r", "l" } },
diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
index efc506b..85e9929 100644
--- a/tcg/aarch64/tcg-target.h
+++ b/tcg/aarch64/tcg-target.h
@@ -56,7 +56,7 @@ typedef enum {
 #define TCG_TARGET_HAS_nand_i32         0
 #define TCG_TARGET_HAS_nor_i32          0
 #define TCG_TARGET_HAS_deposit_i32      0
-#define TCG_TARGET_HAS_movcond_i32      0
+#define TCG_TARGET_HAS_movcond_i32      1
 #define TCG_TARGET_HAS_add2_i32         0
 #define TCG_TARGET_HAS_sub2_i32         0
 #define TCG_TARGET_HAS_mulu2_i32        0
@@ -84,7 +84,7 @@ typedef enum {
 #define TCG_TARGET_HAS_nand_i64         0
 #define TCG_TARGET_HAS_nor_i64          0
 #define TCG_TARGET_HAS_deposit_i64      0
-#define TCG_TARGET_HAS_movcond_i64      0
+#define TCG_TARGET_HAS_movcond_i64      1
 #define TCG_TARGET_HAS_add2_i64         0
 #define TCG_TARGET_HAS_sub2_i64         0
 #define TCG_TARGET_HAS_mulu2_i64        0
-- 
1.8.3.1