From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34729) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxoV-0001m0-RU for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VKxoP-00048w-QP for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:35 -0400 Received: from mail-pa0-x232.google.com ([2607:f8b0:400e:c03::232]:51583) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxoP-00048q-JL for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:29 -0400 Received: by mail-pa0-f50.google.com with SMTP id fb10so3891545pad.37 for ; Sat, 14 Sep 2013 14:55:28 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sat, 14 Sep 2013 14:54:40 -0700 Message-Id: <1379195690-6509-24-git-send-email-rth@twiddle.net> In-Reply-To: <1379195690-6509-1-git-send-email-rth@twiddle.net> References: <1379195690-6509-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v4 23/33] tcg-aarch64: Use ORRI in tcg_out_movi List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, claudio.fontana@gmail.com The subset of logical immediates that we support is quite quick to test, and such constants are quite common to want to load. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index cecda05..9effee7 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -573,6 +573,15 @@ static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, type = TCG_TYPE_I32; } + /* Check for bitfield immediates. For the benefit of 32-bit quantities, + use the sign-extended value. That lets us match rotated values such + as 0xff0000ff with the same 64-bit logic matching 0xffffffffff0000ff. + The truncation happens inside tcg_fmt_Rdn_limm. */ + if (is_limm(svalue)) { + tcg_fmt_Rdn_limm(s, INSN_ORRI, type, rd, TCG_REG_XZR, svalue); + return; + } + /* Would it take fewer insns to begin with MOVN? For the value and its inverse, count the number of 16-bit lanes that are 0. For the benefit of 32-bit quantities, compare the zero-extended normal value vs the -- 1.8.3.1