From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34844) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxoi-00027K-Us for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VKxod-0004CN-1v for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:48 -0400 Received: from mail-pb0-x22f.google.com ([2607:f8b0:400e:c01::22f]:46787) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VKxoc-0004C7-Kl for qemu-devel@nongnu.org; Sat, 14 Sep 2013 17:55:42 -0400 Received: by mail-pb0-f47.google.com with SMTP id rr4so2600964pbb.34 for ; Sat, 14 Sep 2013 14:55:41 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Sat, 14 Sep 2013 14:54:49 -0700 Message-Id: <1379195690-6509-33-git-send-email-rth@twiddle.net> In-Reply-To: <1379195690-6509-1-git-send-email-rth@twiddle.net> References: <1379195690-6509-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PATCH v4 32/33] tcg-aarch64: Introduce tcg_out_ldst_pair List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, claudio.fontana@gmail.com Combines 4 other inline functions and tidies the prologue. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c | 84 ++++++++++++++++-------------------------------- 1 file changed, 27 insertions(+), 57 deletions(-) diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c index fa88e4b..94f9ac1 100644 --- a/tcg/aarch64/tcg-target.c +++ b/tcg/aarch64/tcg-target.c @@ -333,6 +333,10 @@ typedef enum { INSN_BLR = 0xd63f0000, INSN_RET = 0xd65f0000, INSN_B_C = 0x54000000, + + /* Load/store instructions */ + INSN_LDP = 0x28400000, + INSN_STP = 0x28000000, } AArch64Insn; static inline enum aarch64_ldst_op_data @@ -1331,56 +1335,6 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int opc) static uint8_t *tb_ret_addr; -/* callee stack use example: - stp x29, x30, [sp,#-32]! - mov x29, sp - stp x1, x2, [sp,#16] - ... - ldp x1, x2, [sp,#16] - ldp x29, x30, [sp],#32 - ret -*/ - -/* push r1 and r2, and alloc stack space for a total of - alloc_n elements (1 element=16 bytes, must be between 1 and 31. */ -static inline void tcg_out_push_pair(TCGContext *s, TCGReg addr, - TCGReg r1, TCGReg r2, int alloc_n) -{ - /* using indexed scaled simm7 STP 0x28800000 | (ext) | 0x01000000 (pre-idx) - | alloc_n * (-1) << 16 | r2 << 10 | addr << 5 | r1 */ - assert(alloc_n > 0 && alloc_n < 0x20); - alloc_n = (-alloc_n) & 0x3f; - tcg_out32(s, 0xa9800000 | alloc_n << 16 | r2 << 10 | addr << 5 | r1); -} - -/* dealloc stack space for a total of alloc_n elements and pop r1, r2. */ -static inline void tcg_out_pop_pair(TCGContext *s, TCGReg addr, - TCGReg r1, TCGReg r2, int alloc_n) -{ - /* using indexed scaled simm7 LDP 0x28c00000 | (ext) | nothing (post-idx) - | alloc_n << 16 | r2 << 10 | addr << 5 | r1 */ - assert(alloc_n > 0 && alloc_n < 0x20); - tcg_out32(s, 0xa8c00000 | alloc_n << 16 | r2 << 10 | addr << 5 | r1); -} - -static inline void tcg_out_store_pair(TCGContext *s, TCGReg addr, - TCGReg r1, TCGReg r2, int idx) -{ - /* using register pair offset simm7 STP 0x29000000 | (ext) - | idx << 16 | r2 << 10 | addr << 5 | r1 */ - assert(idx > 0 && idx < 0x20); - tcg_out32(s, 0xa9000000 | idx << 16 | r2 << 10 | addr << 5 | r1); -} - -static inline void tcg_out_load_pair(TCGContext *s, TCGReg addr, - TCGReg r1, TCGReg r2, int idx) -{ - /* using register pair offset simm7 LDP 0x29400000 | (ext) - | idx << 16 | r2 << 10 | addr << 5 | r1 */ - assert(idx > 0 && idx < 0x20); - tcg_out32(s, 0xa9400000 | idx << 16 | r2 << 10 | addr << 5 | r1); -} - static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg args[TCG_MAX_OP_ARGS], const int const_args[TCG_MAX_OP_ARGS]) @@ -1937,17 +1891,32 @@ static void tcg_target_init(TCGContext *s) + TCG_TARGET_STACK_ALIGN - 1) \ & ~(TCG_TARGET_STACK_ALIGN - 1)) +static void tcg_out_ldst_pair(TCGContext *s, AArch64Insn insn, + TCGReg r1, TCGReg r2, TCGReg base, + tcg_target_long ofs, bool pre, bool w) +{ + insn |= 1u << 31; /* ext */ + insn |= pre << 24; + insn |= w << 23; + + assert(ofs >= -0x200 && ofs < 0x200 && (ofs & 7) == 0); + insn |= (ofs & (0x7f << 3)) << (15 - 3); + + tcg_out32(s, insn | r2 << 10 | base << 5 | r1); +} + static void tcg_target_qemu_prologue(TCGContext *s) { TCGReg r; /* Push (FP, LR) and allocate space for all saved registers. */ - tcg_out_push_pair(s, TCG_REG_SP, TCG_REG_FP, TCG_REG_LR, PUSH_SIZE / 16); + tcg_out_ldst_pair(s, INSN_STP, TCG_REG_FP, TCG_REG_LR, + TCG_REG_SP, -PUSH_SIZE, 1, 1); /* Store callee-preserved regs x19..x28. */ for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) { - int idx = (r - TCG_REG_X19) / 2 + 1; - tcg_out_store_pair(s, TCG_REG_SP, r, r + 1, idx); + int ofs = (r - TCG_REG_X19 + 2) * 8; + tcg_out_ldst_pair(s, INSN_STP, r, r + 1, TCG_REG_SP, ofs, 1, 0); } /* Make stack space for TCG locals. */ @@ -1976,12 +1945,13 @@ static void tcg_target_qemu_prologue(TCGContext *s) /* Restore callee-preserved registers x19..x28. */ for (r = TCG_REG_X19; r <= TCG_REG_X27; r += 2) { - int idx = (r - TCG_REG_X19) / 2 + 1; - tcg_out_load_pair(s, TCG_REG_SP, r, r + 1, idx); + int ofs = (r - TCG_REG_X19 + 2) * 8; + tcg_out_ldst_pair(s, INSN_LDP, r, r + 1, TCG_REG_SP, ofs, 1, 0); } - /* Pop (FP, LR), restore SP to previous frame, return. */ - tcg_out_pop_pair(s, TCG_REG_SP, TCG_REG_FP, TCG_REG_LR, PUSH_SIZE / 16); + /* Pop (FP, LR), restore SP to previous frame. */ + tcg_out_ldst_pair(s, INSN_LDP, TCG_REG_FP, TCG_REG_LR, + TCG_REG_SP, PUSH_SIZE, 0, 1); tcg_out_ret(s, TCG_REG_LR); } -- 1.8.3.1