[Qemu-devel] [PATCH] sPAPR: implement route_intx_to_irq to get gsi of pci device.

[Qemu-devel] [PATCH] sPAPR: implement route_intx_to_irq to get gsi of pci device.

[Liu Ping Fan]

This is useful when pci assignment happens on sPAPR.

Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com>
---
This patch will apply on patches which enable xics in kernel.
---
 hw/intc/xics.c        |  5 +++++
 hw/ppc/spapr_pci.c    | 14 ++++++++++++++
 include/hw/ppc/xics.h |  1 +
 3 files changed, 20 insertions(+)

diff --git a/hw/intc/xics.c b/hw/intc/xics.c
index bb018d1..02cdab8 100644
--- a/hw/intc/xics.c
+++ b/hw/intc/xics.c
@@ -442,6 +442,11 @@ void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
     icp->ics->islsi[irq - icp->ics->offset] = lsi;
 }
 
+int xics_get_irq_offset(XICSState *icp)
+{
+    return icp->ics->offset;
+}
+
 /*
  * Guest interfaces
  */
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index 9b6ee32..6d3657a 100644
--- a/hw/ppc/spapr_pci.c
+++ b/hw/ppc/spapr_pci.c
@@ -432,6 +432,19 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
     qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
 }
 
+static PCIINTxRoute spapr_phb_route_intx_to_irq(void *opaque, int pirq_pin)
+{
+    int gsi;
+    PCIINTxRoute route;
+    sPAPRPHBState *phb = opaque;
+
+    gsi = phb->lsi_table[pirq_pin].irq;
+    gsi += xics_get_irq_offset(spapr->icp);
+    route.mode = PCI_INTX_ENABLED;
+    route.irq = gsi;
+    return route;
+}
+
 /*
  * MSI/MSIX memory region implementation.
  * The handler handles both MSI and MSIX.
@@ -595,6 +608,7 @@ static int spapr_phb_init(SysBusDevice *s)
                            pci_spapr_set_irq, pci_spapr_map_irq, sphb,
                            &sphb->memspace, &sphb->iospace,
                            PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
+    pci_bus_set_route_irq_fn(bus, spapr_phb_route_intx_to_irq);
     phb->bus = bus;
 
     sphb->dma_window_start = 0;
diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
index 66364c5..6ed1f4d 100644
--- a/include/hw/ppc/xics.h
+++ b/include/hw/ppc/xics.h
@@ -97,6 +97,7 @@ struct ICSIRQState {
 
 qemu_irq xics_get_qirq(XICSState *icp, int irq);
 void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
+int xics_get_irq_offset(XICSState *icp);
 
 void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
 
-- 
1.8.1.4

Re: [Qemu-devel] [PATCH] sPAPR: implement route_intx_to_irq to get gsi of pci device.

[Alexander Graf]

Am 22.09.2013 um 13:47 schrieb Liu Ping Fan <qemulist@gmail.com>:

> This is useful when pci assignment happens on sPAPR.

This patch doesn't sound useful on its own to me, thus probably belongs in a greater patch set.

And without even a clear commit message that explains why exactly this is going to be "useful" eventually I don't see any reason to apply this patch.


Alex

Re: [Qemu-devel] [PATCH] sPAPR: implement route_intx_to_irq to get gsi of pci device.

[liu ping fan]

On Mon, Sep 23, 2013 at 4:02 AM, Alexander Graf <agraf@suse.de> wrote:
>
> Am 22.09.2013 um 13:47 schrieb Liu Ping Fan <qemulist@gmail.com>:
>
>> This is useful when pci assignment happens on sPAPR.
>
> This patch doesn't sound useful on its own to me, thus probably belongs in a greater patch set.
>
Yes, I think, it will be applied after Alexey Kardashevskiy's
patch-set, "[PATCH v4 00/12] xics: reworks and in-kernel support"
CCing Alexey Kardashevskiy

> And without even a clear commit message that explains why exactly this is going to be "useful" eventually I don't see any reason to apply this patch.
>
Pci assignment adopts irqfd in kernel, which need gsi as input param, right?

Thanks,
Pingfan

Re: [Qemu-devel] [PATCH] sPAPR: implement route_intx_to_irq to get gsi of pci device.

[Alexey Kardashevskiy]

On 09/22/2013 09:47 PM, Liu Ping Fan wrote:
> This is useful when pci assignment happens on sPAPR.


I have almost the same patch in my queue already, it will enable irqfd for
both INTX and MSI, I am just waiting till in-kernel XICS patchset gets in
upstream and then I'll post it.


> Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com>
> ---
> This patch will apply on patches which enable xics in kernel.
> ---
>  hw/intc/xics.c        |  5 +++++
>  hw/ppc/spapr_pci.c    | 14 ++++++++++++++
>  include/hw/ppc/xics.h |  1 +
>  3 files changed, 20 insertions(+)
> 
> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
> index bb018d1..02cdab8 100644
> --- a/hw/intc/xics.c
> +++ b/hw/intc/xics.c
> @@ -442,6 +442,11 @@ void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
>      icp->ics->islsi[irq - icp->ics->offset] = lsi;
>  }
>  
> +int xics_get_irq_offset(XICSState *icp)
> +{
> +    return icp->ics->offset;
> +}
> +
>  /*
>   * Guest interfaces
>   */
> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
> index 9b6ee32..6d3657a 100644
> --- a/hw/ppc/spapr_pci.c
> +++ b/hw/ppc/spapr_pci.c
> @@ -432,6 +432,19 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
>      qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
>  }
>  
> +static PCIINTxRoute spapr_phb_route_intx_to_irq(void *opaque, int pirq_pin)
> +{
> +    int gsi;
> +    PCIINTxRoute route;
> +    sPAPRPHBState *phb = opaque;
> +
> +    gsi = phb->lsi_table[pirq_pin].irq;
> +    gsi += xics_get_irq_offset(spapr->icp);


Why do you need this? lsi_table[].irq is received from spapr_allocate_lsi()
which already adds this offset.



> +    route.mode = PCI_INTX_ENABLED;
> +    route.irq = gsi;
> +    return route;
> +}
> +
>  /*
>   * MSI/MSIX memory region implementation.
>   * The handler handles both MSI and MSIX.
> @@ -595,6 +608,7 @@ static int spapr_phb_init(SysBusDevice *s)
>                             pci_spapr_set_irq, pci_spapr_map_irq, sphb,
>                             &sphb->memspace, &sphb->iospace,
>                             PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
> +    pci_bus_set_route_irq_fn(bus, spapr_phb_route_intx_to_irq);
>      phb->bus = bus;
>  
>      sphb->dma_window_start = 0;
> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
> index 66364c5..6ed1f4d 100644
> --- a/include/hw/ppc/xics.h
> +++ b/include/hw/ppc/xics.h
> @@ -97,6 +97,7 @@ struct ICSIRQState {
>  
>  qemu_irq xics_get_qirq(XICSState *icp, int irq);
>  void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
> +int xics_get_irq_offset(XICSState *icp);
>  
>  void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
>  
> 


-- 
Alexey

Re: [Qemu-devel] [PATCH] sPAPR: implement route_intx_to_irq to get gsi of pci device.

[liu ping fan]

On Mon, Sep 23, 2013 at 9:59 AM, Alexey Kardashevskiy <aik@ozlabs.ru> wrote:
> On 09/22/2013 09:47 PM, Liu Ping Fan wrote:
>> This is useful when pci assignment happens on sPAPR.
>
>
> I have almost the same patch in my queue already, it will enable irqfd for
> both INTX and MSI, I am just waiting till in-kernel XICS patchset gets in
> upstream and then I'll post it.
>
Ok,
>
>> Signed-off-by: Liu Ping Fan <pingfank@linux.vnet.ibm.com>
>> ---
>> This patch will apply on patches which enable xics in kernel.
>> ---
>>  hw/intc/xics.c        |  5 +++++
>>  hw/ppc/spapr_pci.c    | 14 ++++++++++++++
>>  include/hw/ppc/xics.h |  1 +
>>  3 files changed, 20 insertions(+)
>>
>> diff --git a/hw/intc/xics.c b/hw/intc/xics.c
>> index bb018d1..02cdab8 100644
>> --- a/hw/intc/xics.c
>> +++ b/hw/intc/xics.c
>> @@ -442,6 +442,11 @@ void xics_set_irq_type(XICSState *icp, int irq, bool lsi)
>>      icp->ics->islsi[irq - icp->ics->offset] = lsi;
>>  }
>>
>> +int xics_get_irq_offset(XICSState *icp)
>> +{
>> +    return icp->ics->offset;
>> +}
>> +
>>  /*
>>   * Guest interfaces
>>   */
>> diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
>> index 9b6ee32..6d3657a 100644
>> --- a/hw/ppc/spapr_pci.c
>> +++ b/hw/ppc/spapr_pci.c
>> @@ -432,6 +432,19 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level)
>>      qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level);
>>  }
>>
>> +static PCIINTxRoute spapr_phb_route_intx_to_irq(void *opaque, int pirq_pin)
>> +{
>> +    int gsi;
>> +    PCIINTxRoute route;
>> +    sPAPRPHBState *phb = opaque;
>> +
>> +    gsi = phb->lsi_table[pirq_pin].irq;
>> +    gsi += xics_get_irq_offset(spapr->icp);
>
>
> Why do you need this? lsi_table[].irq is received from spapr_allocate_lsi()
> which already adds this offset.
>
Oh, you are right, next_irq begin at XICS_IRQ_BASE

Thx,
Pingfan
>
>
>> +    route.mode = PCI_INTX_ENABLED;
>> +    route.irq = gsi;
>> +    return route;
>> +}
>> +
>>  /*
>>   * MSI/MSIX memory region implementation.
>>   * The handler handles both MSI and MSIX.
>> @@ -595,6 +608,7 @@ static int spapr_phb_init(SysBusDevice *s)
>>                             pci_spapr_set_irq, pci_spapr_map_irq, sphb,
>>                             &sphb->memspace, &sphb->iospace,
>>                             PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS);
>> +    pci_bus_set_route_irq_fn(bus, spapr_phb_route_intx_to_irq);
>>      phb->bus = bus;
>>
>>      sphb->dma_window_start = 0;
>> diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h
>> index 66364c5..6ed1f4d 100644
>> --- a/include/hw/ppc/xics.h
>> +++ b/include/hw/ppc/xics.h
>> @@ -97,6 +97,7 @@ struct ICSIRQState {
>>
>>  qemu_irq xics_get_qirq(XICSState *icp, int irq);
>>  void xics_set_irq_type(XICSState *icp, int irq, bool lsi);
>> +int xics_get_irq_offset(XICSState *icp);
>>
>>  void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu);
>>
>>
>
>
> --
> Alexey