From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49066) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VNi98-0002MD-LP for qemu-devel@nongnu.org; Sun, 22 Sep 2013 07:48:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VNi90-0001lm-7g for qemu-devel@nongnu.org; Sun, 22 Sep 2013 07:48:14 -0400 Received: from mail-pd0-x231.google.com ([2607:f8b0:400e:c02::231]:63521) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VNi8z-0001le-VO for qemu-devel@nongnu.org; Sun, 22 Sep 2013 07:48:06 -0400 Received: by mail-pd0-f177.google.com with SMTP id y10so2124003pdj.8 for ; Sun, 22 Sep 2013 04:48:05 -0700 (PDT) From: Liu Ping Fan Date: Sun, 22 Sep 2013 19:47:58 +0800 Message-Id: <1379850478-4289-1-git-send-email-pingfank@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH] sPAPR: implement route_intx_to_irq to get gsi of pci device. List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Alexander Graf , Anthony Liguori This is useful when pci assignment happens on sPAPR. Signed-off-by: Liu Ping Fan --- This patch will apply on patches which enable xics in kernel. --- hw/intc/xics.c | 5 +++++ hw/ppc/spapr_pci.c | 14 ++++++++++++++ include/hw/ppc/xics.h | 1 + 3 files changed, 20 insertions(+) diff --git a/hw/intc/xics.c b/hw/intc/xics.c index bb018d1..02cdab8 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -442,6 +442,11 @@ void xics_set_irq_type(XICSState *icp, int irq, bool lsi) icp->ics->islsi[irq - icp->ics->offset] = lsi; } +int xics_get_irq_offset(XICSState *icp) +{ + return icp->ics->offset; +} + /* * Guest interfaces */ diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 9b6ee32..6d3657a 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -432,6 +432,19 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); } +static PCIINTxRoute spapr_phb_route_intx_to_irq(void *opaque, int pirq_pin) +{ + int gsi; + PCIINTxRoute route; + sPAPRPHBState *phb = opaque; + + gsi = phb->lsi_table[pirq_pin].irq; + gsi += xics_get_irq_offset(spapr->icp); + route.mode = PCI_INTX_ENABLED; + route.irq = gsi; + return route; +} + /* * MSI/MSIX memory region implementation. * The handler handles both MSI and MSIX. @@ -595,6 +608,7 @@ static int spapr_phb_init(SysBusDevice *s) pci_spapr_set_irq, pci_spapr_map_irq, sphb, &sphb->memspace, &sphb->iospace, PCI_DEVFN(0, 0), PCI_NUM_PINS, TYPE_PCI_BUS); + pci_bus_set_route_irq_fn(bus, spapr_phb_route_intx_to_irq); phb->bus = bus; sphb->dma_window_start = 0; diff --git a/include/hw/ppc/xics.h b/include/hw/ppc/xics.h index 66364c5..6ed1f4d 100644 --- a/include/hw/ppc/xics.h +++ b/include/hw/ppc/xics.h @@ -97,6 +97,7 @@ struct ICSIRQState { qemu_irq xics_get_qirq(XICSState *icp, int irq); void xics_set_irq_type(XICSState *icp, int irq, bool lsi); +int xics_get_irq_offset(XICSState *icp); void xics_cpu_setup(XICSState *icp, PowerPCCPU *cpu); -- 1.8.1.4