From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:35397) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOuJo-0000gU-0X for qemu-devel@nongnu.org; Wed, 25 Sep 2013 15:00:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VOuJg-0008Un-O3 for qemu-devel@nongnu.org; Wed, 25 Sep 2013 15:00:11 -0400 Received: from ssl.serverraum.org ([2a01:4f8:a0:1283::1:2]:52241) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VOuJg-0008Nm-9q for qemu-devel@nongnu.org; Wed, 25 Sep 2013 15:00:04 -0400 From: Michael Walle Date: Wed, 25 Sep 2013 20:59:29 +0200 Message-Id: <1380135572-25095-9-git-send-email-michael@walle.cc> In-Reply-To: <1380135572-25095-1-git-send-email-michael@walle.cc> References: <1380135572-25095-1-git-send-email-michael@walle.cc> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 08/11] target-lm32: move model features to LM32CPU List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Michael Walle , =?UTF-8?q?Andreas=20F=C3=A4rber?= This allows us to completely remove CPULM32State from DisasContext. Instead, copy the fields we need to DisasContext. Cc: Andreas F=C3=A4rber Signed-off-by: Michael Walle --- target-lm32/cpu-qom.h | 1 + target-lm32/cpu.h | 12 +++++++++--- target-lm32/helper.c | 15 ++------------- target-lm32/translate.c | 24 ++++++++++++------------ 4 files changed, 24 insertions(+), 28 deletions(-) diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h index 723f604..9f4e233 100644 --- a/target-lm32/cpu-qom.h +++ b/target-lm32/cpu-qom.h @@ -60,6 +60,7 @@ typedef struct LM32CPU { /*< public >*/ =20 CPULM32State env; + const LM32Def *def; } LM32CPU; =20 static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env) diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index dbfe043..67a785e 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -149,6 +149,15 @@ enum { LM32_FLAG_IGNORE_MSB =3D 1, }; =20 +typedef struct { + const char *name; + uint32_t revision; + uint8_t num_interrupts; + uint8_t num_breakpoints; + uint8_t num_watchpoints; + uint32_t features; +} LM32Def; + struct CPULM32State { /* general registers */ uint32_t regs[32]; @@ -177,10 +186,7 @@ struct CPULM32State { DeviceState *juart_state; =20 /* processor core features */ - uint32_t features; uint32_t flags; - uint8_t num_bps; - uint8_t num_wps; =20 }; =20 diff --git a/target-lm32/helper.c b/target-lm32/helper.c index 15bc615..383bcf3 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -90,15 +90,6 @@ void lm32_cpu_do_interrupt(CPUState *cs) } } =20 -typedef struct { - const char *name; - uint32_t revision; - uint8_t num_interrupts; - uint8_t num_breakpoints; - uint8_t num_watchpoints; - uint32_t features; -} LM32Def; - static const LM32Def lm32_defs[] =3D { { .name =3D "lm32-basic", @@ -214,11 +205,9 @@ LM32CPU *cpu_lm32_init(const char *cpu_model) } =20 cpu =3D LM32_CPU(object_new(TYPE_LM32_CPU)); - env =3D &cpu->env; + cpu->def =3D def; =20 - env->features =3D def->features; - env->num_bps =3D def->num_breakpoints; - env->num_wps =3D def->num_watchpoints; + env =3D &cpu->env; env->cfg =3D cfg_by_def(def); =20 object_property_set_bool(OBJECT(cpu), true, "realized", NULL); diff --git a/target-lm32/translate.c b/target-lm32/translate.c index 1d94d52..c8c862e 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -64,7 +64,7 @@ enum { =20 /* This is the state at translation time. */ typedef struct DisasContext { - CPULM32State *env; + const LM32Def *def; target_ulong pc; =20 /* Decoder. */ @@ -420,7 +420,7 @@ static void dec_divu(DisasContext *dc) =20 LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); =20 - if (!(dc->env->features & LM32_FEATURE_DIVIDE)) { + if (!(dc->def->features & LM32_FEATURE_DIVIDE)) { qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not availabl= e\n"); return; } @@ -499,7 +499,7 @@ static void dec_modu(DisasContext *dc) =20 LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1); =20 - if (!(dc->env->features & LM32_FEATURE_DIVIDE)) { + if (!(dc->def->features & LM32_FEATURE_DIVIDE)) { qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not availabl= e\n"); return; } @@ -521,7 +521,7 @@ static void dec_mul(DisasContext *dc) LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } =20 - if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) { + if (!(dc->def->features & LM32_FEATURE_MULTIPLY)) { qemu_log_mask(LOG_GUEST_ERROR, "hardware multiplier is not available\n"); return; @@ -675,7 +675,7 @@ static void dec_sextb(DisasContext *dc) { LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0); =20 - if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) { + if (!(dc->def->features & LM32_FEATURE_SIGN_EXTEND)) { qemu_log_mask(LOG_GUEST_ERROR, "hardware sign extender is not available\n"); return; @@ -688,7 +688,7 @@ static void dec_sexth(DisasContext *dc) { LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0); =20 - if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) { + if (!(dc->def->features & LM32_FEATURE_SIGN_EXTEND)) { qemu_log_mask(LOG_GUEST_ERROR, "hardware sign extender is not available\n"); return; @@ -717,7 +717,7 @@ static void dec_sl(DisasContext *dc) LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } =20 - if (!(dc->env->features & LM32_FEATURE_SHIFT)) { + if (!(dc->def->features & LM32_FEATURE_SHIFT)) { qemu_log_mask(LOG_GUEST_ERROR, "hardware shifter is not availabl= e\n"); return; } @@ -740,7 +740,7 @@ static void dec_sr(DisasContext *dc) LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } =20 - if (!(dc->env->features & LM32_FEATURE_SHIFT)) { + if (!(dc->def->features & LM32_FEATURE_SHIFT)) { if (dc->format =3D=3D OP_FMT_RI) { /* TODO: check r1 =3D=3D 1 during runtime */ } else { @@ -770,7 +770,7 @@ static void dec_sru(DisasContext *dc) LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1); } =20 - if (!(dc->env->features & LM32_FEATURE_SHIFT)) { + if (!(dc->def->features & LM32_FEATURE_SHIFT)) { if (dc->format =3D=3D OP_FMT_RI) { /* TODO: check r1 =3D=3D 1 during runtime */ } else { @@ -880,7 +880,7 @@ static void dec_wcsr(DisasContext *dc) case CSR_BP2: case CSR_BP3: no =3D dc->csr - CSR_BP0; - if (dc->env->num_bps <=3D no) { + if (dc->def->num_breakpoints <=3D no) { qemu_log_mask(LOG_GUEST_ERROR, "breakpoint #%i is not available\n", no); break; @@ -892,7 +892,7 @@ static void dec_wcsr(DisasContext *dc) case CSR_WP2: case CSR_WP3: no =3D dc->csr - CSR_WP0; - if (dc->env->num_wps <=3D no) { + if (dc->def->num_watchpoints <=3D no) { qemu_log_mask(LOG_GUEST_ERROR, "watchpoint #%i is not available\n", no); break; @@ -1033,7 +1033,7 @@ void gen_intermediate_code_internal(LM32CPU *cpu, int max_insns; =20 pc_start =3D tb->pc; - dc->env =3D env; + dc->def =3D cpu->def; dc->tb =3D tb; =20 gen_opc_end =3D tcg_ctx.gen_opc_buf + OPC_MAX_SIZE; --=20 1.7.10.4