From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56783) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPIiT-00083H-Fv for qemu-devel@nongnu.org; Thu, 26 Sep 2013 17:03:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VPIiM-0000qG-W3 for qemu-devel@nongnu.org; Thu, 26 Sep 2013 17:03:17 -0400 Received: from mail-pb0-f45.google.com ([209.85.160.45]:47746) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPIiM-0000q3-QE for qemu-devel@nongnu.org; Thu, 26 Sep 2013 17:03:10 -0400 Received: by mail-pb0-f45.google.com with SMTP id mc17so1654040pbc.18 for ; Thu, 26 Sep 2013 14:03:10 -0700 (PDT) From: Christoffer Dall Date: Thu, 26 Sep 2013 14:03:02 -0700 Message-Id: <1380229386-24166-3-git-send-email-christoffer.dall@linaro.org> In-Reply-To: <1380229386-24166-1-git-send-email-christoffer.dall@linaro.org> References: <1380229386-24166-1-git-send-email-christoffer.dall@linaro.org> Subject: [Qemu-devel] [RFC PATCH v2 2/6] hw: arm_gic: Introduce GIC_SET_PRIORITY macro List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org To make the code slightly cleaner to look at and make the save/restore code easier to understand, introduce this macro to set the priority of interrupts. Signed-off-by: Christoffer Dall --- hw/intc/arm_gic.c | 15 ++++++++++----- hw/intc/gic_internal.h | 1 + 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index c7a24d5..7eaa55f 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -169,6 +169,15 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu) return new_irq; } +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val) +{ + if (irq < GIC_INTERNAL) { + s->priority1[irq][cpu] = val; + } else { + s->priority2[(irq) - GIC_INTERNAL] = val; + } +} + void gic_complete_irq(GICState *s, int cpu, int irq) { int update = 0; @@ -444,11 +453,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, irq = (offset - 0x400) + GIC_BASE_IRQ; if (irq >= s->num_irq) goto bad_reg; - if (irq < GIC_INTERNAL) { - s->priority1[irq][cpu] = value; - } else { - s->priority2[irq - GIC_INTERNAL] = value; - } + gic_set_priority(s, cpu, irq, value); } else if (offset < 0xc00) { /* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the * annoying exception of the 11MPCore's GIC. diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index b3788a8..09e7722 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -111,6 +111,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu); void gic_complete_irq(GICState *s, int cpu, int irq); void gic_update(GICState *s); void gic_init_irqs_and_distributor(GICState *s, int num_irq); +void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val); #define TYPE_ARM_GIC_COMMON "arm_gic_common" #define ARM_GIC_COMMON(obj) \ -- 1.7.10.4