From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56826) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPIiY-0008AM-Gn for qemu-devel@nongnu.org; Thu, 26 Sep 2013 17:03:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VPIiS-0000ss-14 for qemu-devel@nongnu.org; Thu, 26 Sep 2013 17:03:22 -0400 Received: from mail-pd0-f179.google.com ([209.85.192.179]:57813) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VPIiR-0000rs-R5 for qemu-devel@nongnu.org; Thu, 26 Sep 2013 17:03:15 -0400 Received: by mail-pd0-f179.google.com with SMTP id v10so1693775pde.10 for ; Thu, 26 Sep 2013 14:03:15 -0700 (PDT) From: Christoffer Dall Date: Thu, 26 Sep 2013 14:03:04 -0700 Message-Id: <1380229386-24166-5-git-send-email-christoffer.dall@linaro.org> In-Reply-To: <1380229386-24166-1-git-send-email-christoffer.dall@linaro.org> References: <1380229386-24166-1-git-send-email-christoffer.dall@linaro.org> Subject: [Qemu-devel] [RFC PATCH v2 4/6] arm_gic: Support setting/getting binary point reg List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kvmarm@lists.cs.columbia.edu, Christoffer Dall , patches@linaro.org Add a binary_point field to the gic emulation structure and support setting/getting this register now when we have it. We don't actually support interrupt grouping yet, oh well. Signed-off-by: Christoffer Dall Changelog [v2]: - Renamed binary_point to bpr and abpr - Added GICC_ABPR read-as-write logic for TCG --- hw/intc/arm_gic.c | 10 +++++++--- hw/intc/arm_gic_common.c | 6 ++++-- hw/intc/gic_internal.h | 7 +++++++ 3 files changed, 18 insertions(+), 5 deletions(-) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 6470d37..d1ddac1 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -578,8 +578,7 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x04: /* Priority mask */ return s->priority_mask[cpu]; case 0x08: /* Binary Point */ - /* ??? Not implemented. */ - return 0; + return s->bpr[cpu]; case 0x0c: /* Acknowledge */ value = gic_acknowledge_irq(s, cpu); value |= (GIC_SGI_SRC(value, cpu) & 0x7) << 10; @@ -588,6 +587,8 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) return s->running_priority[cpu]; case 0x18: /* Highest Pending Interrupt */ return s->current_pending[cpu]; + case 0x1c: /* Aliased Binary Point */ + return s->abpr[cpu]; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_read: Bad offset %x\n", (int)offset); @@ -606,10 +607,13 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) s->priority_mask[cpu] = (value & 0xff); break; case 0x08: /* Binary Point */ - /* ??? Not implemented. */ + s->bpr[cpu] = (value & 0x7); break; case 0x10: /* End Of Interrupt */ return gic_complete_irq(s, cpu, value & 0x3ff); + case 0x1c: /* Aliased Binary Point */ + s->abpr[cpu] = (value & 0x7); + break; default: qemu_log_mask(LOG_GUEST_ERROR, "gic_cpu_write: Bad offset %x\n", (int)offset); diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 0657e8b..5449d77 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -58,8 +58,8 @@ static const VMStateDescription vmstate_gic_irq_state = { static const VMStateDescription vmstate_gic = { .name = "arm_gic", - .version_id = 5, - .minimum_version_id = 5, + .version_id = 6, + .minimum_version_id = 6, .pre_save = gic_pre_save, .post_load = gic_post_load, .fields = (VMStateField[]) { @@ -76,6 +76,8 @@ static const VMStateDescription vmstate_gic = { VMSTATE_UINT16_ARRAY(running_irq, GICState, NCPU), VMSTATE_UINT16_ARRAY(running_priority, GICState, NCPU), VMSTATE_UINT16_ARRAY(current_pending, GICState, NCPU), + VMSTATE_UINT8_ARRAY(bpr, GICState, NCPU), + VMSTATE_UINT8_ARRAY(abpr, GICState, NCPU), VMSTATE_END_OF_LIST() } }; diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h index 5b53242..758b85a 100644 --- a/hw/intc/gic_internal.h +++ b/hw/intc/gic_internal.h @@ -92,6 +92,13 @@ typedef struct GICState { uint16_t running_priority[NCPU]; uint16_t current_pending[NCPU]; + /* We present the GICv2 without security extensions to a guest and + * therefore the guest can configure the GICC_CTLR to configure group 1 + * binary point in the abpr. + */ + uint8_t bpr[NCPU]; + uint8_t abpr[NCPU]; + uint32_t num_cpu; MemoryRegion iomem; /* Distributor */ -- 1.7.10.4