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From: Alexander Graf <agraf@suse.de>
To: qemu-devel@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>,
	Michael Matz <matz@suse.de>,
	C Fontana <claudio.fontana@linaro.org>,
	Dirk Mueller <dmueller@suse.de>,
	Laurent Desnogues <laurent.desnogues@gmail.com>,
	Christoffer Dall <christoffer.dall@linaro.org>,
	Richard Henderson <rth@twiddle.net>
Subject: [Qemu-devel] [PATCH 23/60] AArch64: Add AdvSIMD modified immediate group handling
Date: Fri, 27 Sep 2013 02:48:17 +0200	[thread overview]
Message-ID: <1380242934-20953-24-git-send-email-agraf@suse.de> (raw)
In-Reply-To: <1380242934-20953-1-git-send-email-agraf@suse.de>

This patch adds support for the AdvSIMD modified immediate group with
all its suboperations (movi, orr, fmov, mvni, bic).

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-arm/translate-a64.c | 129 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 129 insertions(+)

diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c
index 9d6edf4..50561cf 100644
--- a/target-arm/translate-a64.c
+++ b/target-arm/translate-a64.c
@@ -1055,6 +1055,127 @@ static void handle_simd3su0(DisasContext *s, uint32_t insn)
     tcg_temp_free_i64(tcg_res);
 }
 
+/* AdvSIMD modified immediate */
+static void handle_simdmodi(DisasContext *s, uint32_t insn)
+{
+    int rd = get_bits(insn, 0, 5);
+    int cmode = get_bits(insn, 12, 4);
+    uint64_t abcdefgh = get_bits(insn, 5, 5) | (get_bits(insn, 16, 3) << 5);
+    bool is_neg = get_bits(insn, 29, 1);
+    bool is_q = get_bits(insn, 30, 1);
+    int freg_offs_d = offsetof(CPUARMState, vfp.regs[rd * 2]);
+    uint64_t imm = 0;
+    int shift, i;
+    TCGv_i64 tcg_op1_1 = tcg_temp_new_i64();
+    TCGv_i64 tcg_op1_2 = tcg_temp_new_i64();
+    TCGv_i64 tcg_res_1 = tcg_temp_new_i64();
+    TCGv_i64 tcg_res_2 = tcg_temp_new_i64();
+    TCGv_i64 tcg_imm;
+
+    switch ((cmode >> 1) & 0x7) {
+    case 0:
+    case 1:
+    case 2:
+    case 3:
+        shift = ((cmode >> 1) & 0x7) * 8;
+        imm = (abcdefgh << shift) | (abcdefgh << (32 + shift));
+        break;
+    case 4:
+    case 5:
+        shift = ((cmode >> 1) & 0x1) * 8;
+        imm = (abcdefgh << shift) |
+              (abcdefgh << (16 + shift)) |
+              (abcdefgh << (32 + shift)) |
+              (abcdefgh << (48 + shift));
+        break;
+    case 6:
+        if (cmode & 1) {
+            imm = (abcdefgh << 8) |
+                  (abcdefgh << 48) |
+                  0x000000ff000000ffULL;
+        } else {
+            imm = (abcdefgh << 16) |
+                  (abcdefgh << 56) |
+                  0x0000ffff0000ffffULL;
+        }
+        break;
+    case 7:
+        if (!(cmode & 1) && !is_neg) {
+            imm = abcdefgh |
+                  (abcdefgh << 8) |
+                  (abcdefgh << 16) |
+                  (abcdefgh << 24) |
+                  (abcdefgh << 32) |
+                  (abcdefgh << 40) |
+                  (abcdefgh << 48) |
+                  (abcdefgh << 56);
+        } else if (!(cmode & 1) && is_neg) {
+            imm = 0;
+            for (i = 0; i < 8; i++) {
+                if ((abcdefgh) & (1 << (7 - i))) {
+                    imm |= 0xffULL << (i * 8);
+                }
+            }
+        } else if (cmode & 1) {
+            shift = is_neg ? 48 : 19;
+            imm = (abcdefgh & 0x1f) << 19;
+            if (abcdefgh & 0x80) {
+                imm |= 0x80000000;
+            }
+            if (!(abcdefgh & 0x40)) {
+                imm |= 0x40000000;
+            }
+            if (abcdefgh & 0x20) {
+                imm |= is_neg ? 0x3fc00000 : 0x3e000000;
+            }
+            imm |= (imm << 32);
+        }
+        shift = ((cmode >> 1) & 0x1) * 8;
+        break;
+    }
+
+    if (is_neg) {
+        imm = ~imm;
+    }
+    tcg_imm = tcg_const_i64(imm);
+
+    tcg_gen_ld_i64(tcg_op1_1, cpu_env, freg_offs_d);
+    if (is_q) {
+        tcg_gen_ld_i64(tcg_op1_2, cpu_env, freg_offs_d + sizeof(float64));
+    } else {
+        tcg_gen_movi_i64(tcg_op1_2, 0);
+    }
+
+    if ((cmode == 0xf) && is_neg && !is_q) {
+        unallocated_encoding(s);
+        return;
+    } else if ((cmode & 1) && is_neg) {
+        /* AND (BIC) */
+        tcg_gen_and_i64(tcg_res_1, tcg_op1_1, tcg_imm);
+        tcg_gen_and_i64(tcg_res_2, tcg_op1_2, tcg_imm);
+    } else if ((cmode & 1) && !is_neg) {
+        /* ORR */
+        tcg_gen_or_i64(tcg_res_1, tcg_op1_1, tcg_imm);
+        tcg_gen_or_i64(tcg_res_2, tcg_op1_2, tcg_imm);
+    } else {
+        /* MOVI */
+        tcg_gen_mov_i64(tcg_res_1, tcg_imm);
+        tcg_gen_mov_i64(tcg_res_2, tcg_imm);
+    }
+
+    tcg_gen_st_i64(tcg_res_1, cpu_env, freg_offs_d);
+    if (!is_q) {
+        tcg_gen_movi_i64(tcg_res_2, 0);
+    }
+    tcg_gen_st_i64(tcg_res_2, cpu_env, freg_offs_d + sizeof(float64));
+
+    tcg_temp_free_i64(tcg_op1_1);
+    tcg_temp_free_i64(tcg_op1_2);
+    tcg_temp_free_i64(tcg_res_1);
+    tcg_temp_free_i64(tcg_res_2);
+    tcg_temp_free_i64(tcg_imm);
+}
+
 void disas_a64_insn(CPUARMState *env, DisasContext *s)
 {
     uint32_t insn;
@@ -1134,6 +1255,14 @@ void disas_a64_insn(CPUARMState *env, DisasContext *s)
             unallocated_encoding(s);
         }
         break;
+    case 0x0f:
+        if (!get_bits(insn, 31, 1) && !get_bits(insn, 19, 5) &&
+            (get_bits(insn, 10, 2) == 1)) {
+            handle_simdmodi(s, insn);
+        } else {
+            unallocated_encoding(s);
+        }
+        break;
     default:
         unallocated_encoding(s);
         break;
-- 
1.7.12.4

  parent reply	other threads:[~2013-09-27  0:49 UTC|newest]

Thread overview: 115+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-09-27  0:47 [Qemu-devel] [PATCH 00/60] AArch64 TCG emulation support Alexander Graf
2013-09-27  0:47 ` [Qemu-devel] [PATCH 01/60] arm: Use symbolic device names for vfp cmp Alexander Graf
2013-09-27  0:47 ` [Qemu-devel] [PATCH 02/60] arm: Give the fpscr rounding modes names Alexander Graf
2013-09-27  0:47 ` [Qemu-devel] [PATCH 03/60] arm: Split VFP cmp from FPSCR setting Alexander Graf
2013-09-27 14:05   ` Richard Henderson
2013-09-27 22:38     ` Richard Henderson
2013-09-27  0:47 ` [Qemu-devel] [PATCH 04/60] arm: Add AArch64 disassembler stub Alexander Graf
2013-09-27 14:07   ` Richard Henderson
2013-09-27  0:47 ` [Qemu-devel] [PATCH 05/60] softfloat: Add stubs for int16 conversion Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 06/60] AArch64: Add set_pc cpu method Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 07/60] ARM: Add 64bit VFP handling Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 08/60] AArch64: Add support to print VFP registers in CPU Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 09/60] AArch64: Add b and bl handling Alexander Graf
2013-09-27  9:11   ` Claudio Fontana
2013-09-27 14:40   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 10/60] AArch64: Add handling for br instructions Alexander Graf
2013-09-27 14:51   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 11/60] AArch64: Add STP instruction emulation Alexander Graf
2013-09-27 17:38   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 12/60] AArch64: Add ldarx style " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 13/60] AArch64: Add stubs for a64 specific helpers Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 14/60] AArch64: Add orr instruction emulation Alexander Graf
2013-09-27 18:25   ` Richard Henderson
2013-10-31  0:29     ` Alexander Graf
2013-10-31  1:44       ` Peter Maydell
2013-11-18 10:15     ` Claudio Fontana
2013-11-18 10:37       ` Laurent Desnogues
2013-11-18 13:12       ` Michael Matz
2013-11-18 13:15         ` Peter Maydell
2013-11-18 13:24           ` Claudio Fontana
2013-11-18 13:46           ` Michael Matz
2013-11-18 13:49             ` Peter Maydell
2013-11-18 13:43         ` Claudio Fontana
2013-11-18 13:44           ` Peter Maydell
2013-11-18 13:55           ` Michael Matz
2013-11-18 19:51             ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 15/60] AArch64: Add add instruction family emulation Alexander Graf
2013-09-27 18:51   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 16/60] AArch64: Add emulation for SIMD ld/st multiple Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 17/60] AArch64: Add dup GPR->Vec instruction emulation Alexander Graf
2013-09-27 18:55   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 18/60] AArch64: Add umov " Alexander Graf
2013-09-27 18:56   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 19/60] AArch64: Add ins GPR->Vec " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 20/60] AArch64: Add SIMD ORR family " Alexander Graf
2013-09-27 19:21   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 21/60] AArch64: Convert SIMD load/store to common function Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 22/60] AArch64: Add AdvSIMD scalar three same group handling Alexander Graf
2013-09-27 19:24   ` Richard Henderson
2013-09-27  0:48 ` Alexander Graf [this message]
2013-11-19 20:23   ` [Qemu-devel] [PATCH 23/60] AArch64: Add AdvSIMD modified immediate " Janne Grunau
2013-09-27  0:48 ` [Qemu-devel] [PATCH 24/60] AArch64: Add SIMD ushll instruction emulation Alexander Graf
2013-09-27 19:29   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 25/60] AArch64: Add SIMD shl " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 26/60] AArch64: Add ADR " Alexander Graf
2013-11-19 17:17   ` Claudio Fontana
2013-11-19 17:52     ` Claudio Fontana
2013-11-19 18:03       ` Peter Maydell
2013-11-19 18:09         ` Peter Maydell
2013-11-20 14:40     ` Michael Matz
2013-09-27  0:48 ` [Qemu-devel] [PATCH 27/60] AArch64: Add addi " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 28/60] AArch64: Add movi " Alexander Graf
2013-09-27 19:38   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 29/60] AArch64: Add orri " Alexander Graf
2013-09-27 19:42   ` Richard Henderson
2013-11-26 11:56     ` Claudio Fontana
2013-11-26 12:05       ` Laurent Desnogues
2013-11-27 21:56       ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 30/60] AArch64: Add extr " Alexander Graf
2013-09-27 19:45   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 31/60] AArch64: Add bfm family " Alexander Graf
2013-09-27 20:01   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 32/60] AArch64: Add svc " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 33/60] AArch64: Add bc " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 34/60] AArch64: Add b.cond " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 35/60] AArch64: Add mrs " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 36/60] AArch64: Add msr " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 37/60] AArch64: Add hint " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 38/60] AArch64: Add stub barrier " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 39/60] AArch64: Add stub sys " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 40/60] AArch64: Add tbz " Alexander Graf
2013-09-27 20:50   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 41/60] AArch64: Add ldr/str instruction family emulation Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 42/60] AArch64: Add literal ld instruction emulation Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 43/60] AArch64: Add cinc " Alexander Graf
2013-09-27 20:52   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 44/60] AArch64: Add division instruction family emulation Alexander Graf
2013-09-27 20:54   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 45/60] AArch64: Add shift " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 46/60] AArch64: Add rev " Alexander Graf
2013-09-27 21:07   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 47/60] AArch64: Add clz instruction emulation Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 48/60] AArch64: Add 0x1a encoding of add instructions Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 49/60] AArch64: Add "Data-processing (3 source)" instruction Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 50/60] AArch64: Add "Floating-point<->fixed-point Alexander Graf
2013-11-19 20:41   ` Janne Grunau
2013-11-20 14:47     ` Michael Matz
2013-11-21 12:34       ` Janne Grunau
2013-11-21 12:40         ` Peter Maydell
2013-09-27  0:48 ` [Qemu-devel] [PATCH 51/60] AArch64: Add fmov (scalar, immediate) instruction Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 52/60] AArch64: Add "Floating-point<->integer conversions" Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 53/60] AArch64: Add "Floating-point compare" instruction Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 54/60] AArch64: Add "Floating-point data-processing (1 Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 55/60] " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 56/60] AArch64: Add "Floating-point data-processing (2 Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 57/60] " Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 58/60] AArch64: Add "ADD (vector)" instruction emulation Alexander Graf
2013-09-27  0:48 ` [Qemu-devel] [PATCH 59/60] AArch64: Add "Floating-point data-processing (3 Alexander Graf
2013-09-27 21:34   ` Richard Henderson
2013-09-27  0:48 ` [Qemu-devel] [PATCH 60/60] " Alexander Graf
2013-09-27  1:02 ` [Qemu-devel] [PATCH 00/60] AArch64 TCG emulation support Alexander Graf
2013-09-27  2:30   ` Peter Maydell
2013-09-27 10:39     ` Alexander Graf
2013-10-16 19:54 ` Edgar E. Iglesias
2013-10-17 12:23   ` Alexander Graf

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