[Qemu-devel] [PATCH 02/60] arm: Give the fpscr rounding modes names

[Alexander Graf <agraf@suse.de>]

When setting rounding modes we currently just hardcode the numeric values
for rounding modes in a big switch statement.

With AArch64 support coming, we will need to refer to these rounding modes
at different places throughout the code though, so let's better give them
names so we don't get confused by accident.

Signed-off-by: Alexander Graf <agraf@suse.de>
---
 target-arm/cpu.h    | 5 +++++
 target-arm/helper.c | 8 ++++----
 2 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index ce835ef..e69bb74 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -315,6 +315,11 @@ static inline bool is_a64(CPUARMState *env)
 #define PSTATE_V_SHIFT 0
 #define PSTATE_V  (1 << PSTATE_V_SHIFT)
 
+#define ROUND_MODE_TIEEVEN  0
+#define ROUND_MODE_UP       1
+#define ROUND_MODE_DOWN     2
+#define ROUND_MODE_ZERO     3
+
 /* you can call this signal handler from your SIGBUS and SIGSEGV
    signal handlers to inform the virtual CPU of exceptions. non zero
    is returned if the signal was handled by the virtual CPU.  */
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 3ec56d6..24e8ae4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3521,16 +3521,16 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
     if (changed & (3 << 22)) {
         i = (val >> 22) & 3;
         switch (i) {
-        case 0:
+        case ROUND_MODE_TIEEVEN:
             i = float_round_nearest_even;
             break;
-        case 1:
+        case ROUND_MODE_UP:
             i = float_round_up;
             break;
-        case 2:
+        case ROUND_MODE_DOWN:
             i = float_round_down;
             break;
-        case 3:
+        case ROUND_MODE_ZERO:
             i = float_round_to_zero;
             break;
         }
-- 
1.7.12.4