From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:54605) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VQEg1-00034j-3G for qemu-devel@nongnu.org; Sun, 29 Sep 2013 06:56:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VQEfv-0007Nz-3j for qemu-devel@nongnu.org; Sun, 29 Sep 2013 06:56:37 -0400 Received: from mx1.redhat.com ([209.132.183.28]:8460) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VQEfu-0007Mr-QW for qemu-devel@nongnu.org; Sun, 29 Sep 2013 06:56:31 -0400 Date: Sun, 29 Sep 2013 13:58:49 +0300 From: "Michael S. Tsirkin" Message-ID: <1380452123-5989-11-git-send-email-mst@redhat.com> References: <1380452123-5989-1-git-send-email-mst@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1380452123-5989-1-git-send-email-mst@redhat.com> Subject: [Qemu-devel] [PATCH v6 10/26] q35: expose mmcfg size as a property List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com, afaerber@suse.de, kraxel@redhat.com Address is already exposed, expose size for symmetry. Signed-off-by: Michael S. Tsirkin --- include/hw/pci/pcie_host.h | 1 + hw/pci-host/q35.c | 14 ++++++++++++++ 2 files changed, 15 insertions(+) diff --git a/include/hw/pci/pcie_host.h b/include/hw/pci/pcie_host.h index 33d75bd..acca45e 100644 --- a/include/hw/pci/pcie_host.h +++ b/include/hw/pci/pcie_host.h @@ -29,6 +29,7 @@ OBJECT_CHECK(PCIExpressHost, (obj), TYPE_PCIE_HOST_BRIDGE) #define PCIE_HOST_MCFG_BASE "MCFG" +#define PCIE_HOST_MCFG_SIZE "mcfg_size" /* pcie_host::base_addr == PCIE_BASE_ADDR_UNMAPPED when it isn't mapped. */ #define PCIE_BASE_ADDR_UNMAPPED ((hwaddr)-1ULL) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index e46f286..a051b58 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -109,6 +109,16 @@ static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, visit_type_uint64(v, &w64.end, name, errp); } +static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, + void *opaque, const char *name, + Error **errp) +{ + PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); + uint32_t value = e->size; + + visit_type_uint32(v, &value, name, errp); +} + static Property mch_props[] = { DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), @@ -160,6 +170,10 @@ static void q35_host_initfn(Object *obj) q35_host_get_pci_hole64_end, NULL, NULL, NULL, NULL); + object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", + q35_host_get_mmcfg_size, + NULL, NULL, NULL, NULL); + /* Leave enough space for the biggest MCFG BAR */ /* TODO: this matches current bios behaviour, but * it's not a power of two, which means an MTRR -- MST