From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:53701) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VR7YE-00052j-OV for qemu-devel@nongnu.org; Tue, 01 Oct 2013 17:32:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VR7Y8-0006du-OO for qemu-devel@nongnu.org; Tue, 01 Oct 2013 17:32:14 -0400 Received: from mail-pa0-x229.google.com ([2607:f8b0:400e:c03::229]:42180) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VR7Y8-0006dj-HR for qemu-devel@nongnu.org; Tue, 01 Oct 2013 17:32:08 -0400 Received: by mail-pa0-f41.google.com with SMTP id bj1so75130pad.28 for ; Tue, 01 Oct 2013 14:32:07 -0700 (PDT) Sender: Richard Henderson From: Richard Henderson Date: Tue, 1 Oct 2013 14:31:45 -0700 Message-Id: <1380663109-14434-5-git-send-email-rth@twiddle.net> In-Reply-To: <1380663109-14434-1-git-send-email-rth@twiddle.net> References: <1380663109-14434-1-git-send-email-rth@twiddle.net> Subject: [Qemu-devel] [PULL 4/8] tcg-arm: Use QEMU_BUILD_BUG_ON to verify constraints on tlb List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net, anthony@codemonkey.ws One of the two constraints we already checked via #if, but the tlb offset distance was only checked at runtime. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index f953f4e..1f7bbe1 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1163,6 +1163,15 @@ static TCGReg tcg_out_arg_reg64(TCGContext *s, TCGReg argreg, #define TLB_SHIFT (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS) +/* We're expecting to use an 8-bit immediate and to mask. */ +QEMU_BUILD_BUG_ON(CPU_TLB_BITS > 8); + +/* We're expecting to use an 8-bit immediate add + 8-bit ldrd offset. + Using the offset of the second entry in the last tlb table ensures + that we can index all of the elements of the first entry. */ +QEMU_BUILD_BUG_ON(offsetof(CPUArchState, tlb_table[NB_MMU_MODES - 1][1]) + > 0xffff); + /* Load and compare a TLB entry, leaving the flags set. Leaves R2 pointing to the tlb entry. Clobbers R1 and TMP. */ @@ -1190,14 +1199,10 @@ static void tcg_out_tlb_read(TCGContext *s, TCGReg addrlo, TCGReg addrhi, * ldr r0, [r2, r0]! (3) * cmp r0, tmp (4) */ -# if CPU_TLB_BITS > 8 -# error -# endif tcg_out_dat_reg(s, COND_AL, ARITH_MOV, TCG_REG_TMP, 0, addrlo, SHIFT_IMM_LSR(TARGET_PAGE_BITS)); - /* We assume that the offset is contained within 16 bits. */ - assert((tlb_offset & ~0xffff) == 0); + /* We checked that the offset is contained within 16 bits above. */ if (tlb_offset > 0xff) { tcg_out_dat_imm(s, COND_AL, ARITH_ADD, TCG_REG_R2, base, (24 << 7) | (tlb_offset >> 8)); -- 1.8.1.4