From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:47870) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VT5NA-000092-1q for qemu-devel@nongnu.org; Mon, 07 Oct 2013 03:37:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VT5N3-0007vv-Pv for qemu-devel@nongnu.org; Mon, 07 Oct 2013 03:36:55 -0400 Received: from mx1.redhat.com ([209.132.183.28]:7473) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VT5N3-0007vj-E4 for qemu-devel@nongnu.org; Mon, 07 Oct 2013 03:36:49 -0400 From: Marcel Apfelbaum Date: Mon, 7 Oct 2013 10:36:37 +0300 Message-Id: <1381131401-15155-5-git-send-email-marcel.a@redhat.com> In-Reply-To: <1381131401-15155-1-git-send-email-marcel.a@redhat.com> References: <1381131401-15155-1-git-send-email-marcel.a@redhat.com> Subject: [Qemu-devel] [PATCH v3 4/8] hw/vmxnet3: set interrupts using pci irq wrappers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: kwolf@redhat.com, peter.maydell@linaro.org, peter.crosthwaite@xilinx.com, anthony@codemonkey.ws, mst@redhat.com, sw@weilnetz.de, jasowang@redhat.com, dkoch@verizon.com, keith.busch@intel.com, alex.williamson@redhat.com, kraxel@redhat.com, stefanha@redhat.com, dmitry@daynix.com, pbonzini@redhat.com, afaerber@suse.de, ehabkost@redhat.com pci_set_irq uses PCI_INTERRUPT_PIN config register to compute device INTx pin to assert/deassert. An assert is used to ensure that intx received from the quest OS corresponds to PCI_INTERRUPT_PIN. Signed-off-by: Marcel Apfelbaum --- Changes from v2: - Addressed Alex Williamson's comments - replaced calls to pci_set_irq with pci_irq_assert/deassert when possible - fixed a deassert replaced by an assert by mistake hw/net/vmxnet3.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c index 49c2466..19687aa 100644 --- a/hw/net/vmxnet3.c +++ b/hw/net/vmxnet3.c @@ -336,7 +336,7 @@ static bool _vmxnet3_assert_interrupt_line(VMXNET3State *s, uint32_t int_idx) } VMW_IRPRN("Asserting line for interrupt %u", int_idx); - qemu_set_irq(d->irq[int_idx], 1); + pci_irq_assert(d); return true; } @@ -356,7 +356,7 @@ static void _vmxnet3_deassert_interrupt_line(VMXNET3State *s, int lidx) assert(!s->msi_used || !msi_enabled(d)); VMW_IRPRN("Deasserting line for interrupt %u", lidx); - qemu_set_irq(d->irq[lidx], 0); + pci_irq_deassert(d); } static void vmxnet3_update_interrupt_line_state(VMXNET3State *s, int lidx) @@ -1299,6 +1299,12 @@ static void vmxnet3_update_features(VMXNET3State *s) } } +static bool vmxnet3_verify_intx(VMXNET3State *s, int intx) +{ + return s->msix_used || s->msi_used || (intx == + (pci_get_byte(s->parent_obj.config + PCI_INTERRUPT_PIN) - 1)); +} + static void vmxnet3_activate_device(VMXNET3State *s) { int i; @@ -1332,6 +1338,7 @@ static void vmxnet3_activate_device(VMXNET3State *s) s->event_int_idx = VMXNET3_READ_DRV_SHARED8(s->drv_shmem, devRead.intrConf.eventIntrIdx); + assert(vmxnet3_verify_intx(s, s->event_int_idx)); VMW_CFPRN("Events interrupt line is %u", s->event_int_idx); s->auto_int_masking = @@ -1364,6 +1371,7 @@ static void vmxnet3_activate_device(VMXNET3State *s) /* Read interrupt number for this TX queue */ s->txq_descr[i].intr_idx = VMXNET3_READ_TX_QUEUE_DESCR8(qdescr_pa, conf.intrIdx); + assert(vmxnet3_verify_intx(s, s->txq_descr[i].intr_idx)); VMW_CFPRN("TX Queue %d interrupt: %d", i, s->txq_descr[i].intr_idx); @@ -1411,6 +1419,7 @@ static void vmxnet3_activate_device(VMXNET3State *s) /* Read interrupt number for this RX queue */ s->rxq_descr[i].intr_idx = VMXNET3_READ_TX_QUEUE_DESCR8(qd_pa, conf.intrIdx); + assert(vmxnet3_verify_intx(s, s->rxq_descr[i].intr_idx)); VMW_CFPRN("RX Queue %d interrupt: %d", i, s->rxq_descr[i].intr_idx); -- 1.8.3.1