From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VTbeB-00053y-C7 for qemu-devel@nongnu.org; Tue, 08 Oct 2013 14:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VTbdu-0007ZY-9m for qemu-devel@nongnu.org; Tue, 08 Oct 2013 14:04:39 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43031 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VTbdt-0007X5-Sw for qemu-devel@nongnu.org; Tue, 08 Oct 2013 14:04:22 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 8 Oct 2013 19:44:23 +0200 Message-Id: <1381254296-3203-26-git-send-email-afaerber@suse.de> In-Reply-To: <1381254296-3203-1-git-send-email-afaerber@suse.de> References: <1381254296-3203-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 25/58] a9mpcore: Embed A9SCUState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook From: Andreas F=C3=A4rber Prepares for QOM realize. Reviewed-by: Peter Maydell Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/a9mpcore.c | 16 ++++++++++------ hw/misc/a9scu.c | 18 +----------------- include/hw/misc/a9scu.h | 31 +++++++++++++++++++++++++++++++ 3 files changed, 42 insertions(+), 23 deletions(-) create mode 100644 include/hw/misc/a9scu.h diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index c57b149..df92e3f 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -10,6 +10,7 @@ =20 #include "hw/sysbus.h" #include "hw/intc/arm_gic.h" +#include "hw/misc/a9scu.h" =20 #define TYPE_A9MPCORE_PRIV "a9mpcore_priv" #define A9MPCORE_PRIV(obj) \ @@ -24,10 +25,10 @@ typedef struct A9MPPrivState { MemoryRegion container; DeviceState *mptimer; DeviceState *wdt; - DeviceState *scu; uint32_t num_irq; =20 GICState gic; + A9SCUState scu; } A9MPPrivState; =20 static void a9mp_priv_set_irq(void *opaque, int irq, int level) @@ -46,12 +47,15 @@ static void a9mp_priv_initfn(Object *obj) =20 object_initialize(&s->gic, sizeof(s->gic), TYPE_ARM_GIC); qdev_set_parent_bus(DEVICE(&s->gic), sysbus_get_default()); + + object_initialize(&s->scu, sizeof(s->scu), TYPE_A9_SCU); + qdev_set_parent_bus(DEVICE(&s->scu), sysbus_get_default()); } =20 static int a9mp_priv_init(SysBusDevice *dev) { A9MPPrivState *s =3D A9MPCORE_PRIV(dev); - DeviceState *gicdev; + DeviceState *gicdev, *scudev; SysBusDevice *timerbusdev, *wdtbusdev, *gicbusdev, *scubusdev; int i; =20 @@ -67,10 +71,10 @@ static int a9mp_priv_init(SysBusDevice *dev) /* Pass through inbound GPIO lines to the GIC */ qdev_init_gpio_in(DEVICE(dev), a9mp_priv_set_irq, s->num_irq - 32); =20 - s->scu =3D qdev_create(NULL, "a9-scu"); - qdev_prop_set_uint32(s->scu, "num-cpu", s->num_cpu); - qdev_init_nofail(s->scu); - scubusdev =3D SYS_BUS_DEVICE(s->scu); + scudev =3D DEVICE(&s->scu); + qdev_prop_set_uint32(scudev, "num-cpu", s->num_cpu); + qdev_init_nofail(scudev); + scubusdev =3D SYS_BUS_DEVICE(&s->scu); =20 s->mptimer =3D qdev_create(NULL, "arm_mptimer"); qdev_prop_set_uint32(s->mptimer, "num-cpu", s->num_cpu); diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c index 2661014..4434945 100644 --- a/hw/misc/a9scu.c +++ b/hw/misc/a9scu.c @@ -8,23 +8,7 @@ * This code is licensed under the GPL. */ =20 -#include "hw/sysbus.h" - -/* A9MP private memory region. */ - -typedef struct A9SCUState { - /*< private >*/ - SysBusDevice parent_obj; - /*< public >*/ - - MemoryRegion iomem; - uint32_t control; - uint32_t status; - uint32_t num_cpu; -} A9SCUState; - -#define TYPE_A9_SCU "a9-scu" -#define A9_SCU(obj) OBJECT_CHECK(A9SCUState, (obj), TYPE_A9_SCU) +#include "hw/misc/a9scu.h" =20 static uint64_t a9_scu_read(void *opaque, hwaddr offset, unsigned size) diff --git a/include/hw/misc/a9scu.h b/include/hw/misc/a9scu.h new file mode 100644 index 0000000..efb0c30 --- /dev/null +++ b/include/hw/misc/a9scu.h @@ -0,0 +1,31 @@ +/* + * Cortex-A9MPCore Snoop Control Unit (SCU) emulation. + * + * Copyright (c) 2009 CodeSourcery. + * Copyright (c) 2011 Linaro Limited. + * Written by Paul Brook, Peter Maydell. + * + * This code is licensed under the GPL. + */ +#ifndef HW_MISC_A9SCU_H +#define HW_MISC_A9SCU_H + +#include "hw/sysbus.h" + +/* A9MP private memory region. */ + +typedef struct A9SCUState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + uint32_t control; + uint32_t status; + uint32_t num_cpu; +} A9SCUState; + +#define TYPE_A9_SCU "a9-scu" +#define A9_SCU(obj) OBJECT_CHECK(A9SCUState, (obj), TYPE_A9_SCU) + +#endif --=20 1.8.1.4