From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37903) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VTbe6-00053h-HL for qemu-devel@nongnu.org; Tue, 08 Oct 2013 14:04:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VTbdt-0007XG-Nm for qemu-devel@nongnu.org; Tue, 08 Oct 2013 14:04:34 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43011 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VTbdt-0007Un-8f for qemu-devel@nongnu.org; Tue, 08 Oct 2013 14:04:21 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 8 Oct 2013 19:44:29 +0200 Message-Id: <1381254296-3203-32-git-send-email-afaerber@suse.de> In-Reply-To: <1381254296-3203-1-git-send-email-afaerber@suse.de> References: <1381254296-3203-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 31/58] a15mpcore: Embed GICState List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook From: Andreas F=C3=A4rber This covers both emulated and KVM GIC. Prepares for QOM realize. Reviewed-by: Peter Maydell Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/a15mpcore.c | 39 ++++++++++++++++++++++++--------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index af29c35..b2614e7 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -20,6 +20,7 @@ =20 #include "hw/sysbus.h" #include "sysemu/kvm.h" +#include "hw/intc/arm_gic.h" =20 /* A15MP private memory region. */ =20 @@ -35,41 +36,49 @@ typedef struct A15MPPrivState { uint32_t num_cpu; uint32_t num_irq; MemoryRegion container; - DeviceState *gic; + + GICState gic; } A15MPPrivState; =20 static void a15mp_priv_set_irq(void *opaque, int irq, int level) { A15MPPrivState *s =3D (A15MPPrivState *)opaque; - qemu_set_irq(qdev_get_gpio_in(s->gic, irq), level); + + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->gic), irq), level); } =20 static void a15mp_priv_initfn(Object *obj) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); A15MPPrivState *s =3D A15MPCORE_PRIV(obj); + DeviceState *gicdev; + const char *gictype =3D "arm_gic"; + + if (kvm_irqchip_in_kernel()) { + gictype =3D "kvm-arm-gic"; + } =20 memory_region_init(&s->container, obj, "a15mp-priv-container", 0x800= 0); sysbus_init_mmio(sbd, &s->container); + + object_initialize(&s->gic, sizeof(s->gic), gictype); + gicdev =3D DEVICE(&s->gic); + qdev_set_parent_bus(gicdev, sysbus_get_default()); + qdev_prop_set_uint32(gicdev, "revision", 2); } =20 static int a15mp_priv_init(SysBusDevice *dev) { A15MPPrivState *s =3D A15MPCORE_PRIV(dev); + DeviceState *gicdev; SysBusDevice *busdev; - const char *gictype =3D "arm_gic"; int i; =20 - if (kvm_irqchip_in_kernel()) { - gictype =3D "kvm-arm-gic"; - } - - s->gic =3D qdev_create(NULL, gictype); - qdev_prop_set_uint32(s->gic, "num-cpu", s->num_cpu); - qdev_prop_set_uint32(s->gic, "num-irq", s->num_irq); - qdev_prop_set_uint32(s->gic, "revision", 2); - qdev_init_nofail(s->gic); - busdev =3D SYS_BUS_DEVICE(s->gic); + gicdev =3D DEVICE(&s->gic); + qdev_prop_set_uint32(gicdev, "num-cpu", s->num_cpu); + qdev_prop_set_uint32(gicdev, "num-irq", s->num_irq); + qdev_init_nofail(gicdev); + busdev =3D SYS_BUS_DEVICE(&s->gic); =20 /* Pass through outbound IRQ lines from the GIC */ sysbus_pass_irq(dev, busdev); @@ -87,10 +96,10 @@ static int a15mp_priv_init(SysBusDevice *dev) * since a real A15 always has TrustZone but QEMU doesn't. */ qdev_connect_gpio_out(cpudev, 0, - qdev_get_gpio_in(s->gic, ppibase + 30)); + qdev_get_gpio_in(gicdev, ppibase + 30)); /* virtual timer */ qdev_connect_gpio_out(cpudev, 1, - qdev_get_gpio_in(s->gic, ppibase + 27)); + qdev_get_gpio_in(gicdev, ppibase + 27)); } =20 /* Memory map (addresses are offsets from PERIPHBASE): --=20 1.8.1.4