From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38015) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VTbeC-000541-2B for qemu-devel@nongnu.org; Tue, 08 Oct 2013 14:04:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VTbdu-0007a3-Cs for qemu-devel@nongnu.org; Tue, 08 Oct 2013 14:04:40 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43039 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VTbdt-0007Xt-Vf for qemu-devel@nongnu.org; Tue, 08 Oct 2013 14:04:22 -0400 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Tue, 8 Oct 2013 19:44:42 +0200 Message-Id: <1381254296-3203-45-git-send-email-afaerber@suse.de> In-Reply-To: <1381254296-3203-1-git-send-email-afaerber@suse.de> References: <1381254296-3203-1-git-send-email-afaerber@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Subject: [Qemu-devel] [PULL 44/58] arm11mpcore: Split off RealView MPCore List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?Andreas=20F=C3=A4rber?= , Paul Brook Reviewed-by: Peter Maydell Signed-off-by: Andreas F=C3=A4rber --- hw/cpu/Makefile.objs | 1 + hw/cpu/arm11mpcore.c | 121 ----------------------------------------- hw/cpu/realview_mpcore.c | 139 +++++++++++++++++++++++++++++++++++++++++= ++++++ 3 files changed, 140 insertions(+), 121 deletions(-) create mode 100644 hw/cpu/realview_mpcore.c diff --git a/hw/cpu/Makefile.objs b/hw/cpu/Makefile.objs index df287c1..6381238 100644 --- a/hw/cpu/Makefile.objs +++ b/hw/cpu/Makefile.objs @@ -1,4 +1,5 @@ obj-$(CONFIG_ARM11MPCORE) +=3D arm11mpcore.o +obj-$(CONFIG_REALVIEW) +=3D realview_mpcore.o obj-$(CONFIG_A9MPCORE) +=3D a9mpcore.o obj-$(CONFIG_A15MPCORE) +=3D a15mpcore.o obj-$(CONFIG_ICC_BUS) +=3D icc_bus.o diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 0ec27c7..717d3e4 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -134,126 +134,6 @@ static void mpcore_priv_initfn(Object *obj) qdev_set_parent_bus(DEVICE(&s->wdtimer), sysbus_get_default()); } =20 -#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" -#define REALVIEW_MPCORE_RIRQ(obj) \ - OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ) - -/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ - controllers. The output of these, plus some of the raw input lines - are fed into a single SMP-aware interrupt controller on the CPU. */ -typedef struct { - SysBusDevice parent_obj; - - qemu_irq cpuic[32]; - qemu_irq rvic[4][64]; - uint32_t num_cpu; - - ARM11MPCorePriveState priv; - RealViewGICState gic[4]; -} mpcore_rirq_state; - -/* Map baseboard IRQs onto CPU IRQ lines. */ -static const int mpcore_irq_map[32] =3D { - -1, -1, -1, -1, 1, 2, -1, -1, - -1, -1, 6, -1, 4, 5, -1, -1, - -1, 14, 15, 0, 7, 8, -1, -1, - -1, -1, -1, -1, 9, 3, -1, -1, -}; - -static void mpcore_rirq_set_irq(void *opaque, int irq, int level) -{ - mpcore_rirq_state *s =3D (mpcore_rirq_state *)opaque; - int i; - - for (i =3D 0; i < 4; i++) { - qemu_set_irq(s->rvic[i][irq], level); - } - if (irq < 32) { - irq =3D mpcore_irq_map[irq]; - if (irq >=3D 0) { - qemu_set_irq(s->cpuic[irq], level); - } - } -} - -static void realview_mpcore_realize(DeviceState *dev, Error **errp) -{ - SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); - mpcore_rirq_state *s =3D REALVIEW_MPCORE_RIRQ(dev); - DeviceState *priv =3D DEVICE(&s->priv); - DeviceState *gic; - SysBusDevice *gicbusdev; - Error *err =3D NULL; - int n; - int i; - - qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); - object_property_set_bool(OBJECT(&s->priv), true, "realized", &err); - if (err !=3D NULL) { - error_propagate(errp, err); - return; - } - sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv)); - for (i =3D 0; i < 32; i++) { - s->cpuic[i] =3D qdev_get_gpio_in(priv, i); - } - /* ??? IRQ routing is hardcoded to "normal" mode. */ - for (n =3D 0; n < 4; n++) { - object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &= err); - if (err !=3D NULL) { - error_propagate(errp, err); - return; - } - gic =3D DEVICE(&s->gic[n]); - gicbusdev =3D SYS_BUS_DEVICE(&s->gic[n]); - sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000); - sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]); - for (i =3D 0; i < 64; i++) { - s->rvic[n][i] =3D qdev_get_gpio_in(gic, i); - } - } - qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); -} - -static void mpcore_rirq_init(Object *obj) -{ - SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - mpcore_rirq_state *s =3D REALVIEW_MPCORE_RIRQ(obj); - SysBusDevice *privbusdev; - int i; - - object_initialize(&s->priv, sizeof(s->priv), TYPE_ARM11MPCORE_PRIV); - qdev_set_parent_bus(DEVICE(&s->priv), sysbus_get_default()); - privbusdev =3D SYS_BUS_DEVICE(&s->priv); - sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); - - for (i =3D 0; i < 4; i++) { - object_initialize(&s->gic[i], sizeof(s->gic[i]), TYPE_REALVIEW_G= IC); - qdev_set_parent_bus(DEVICE(&s->gic[i]), sysbus_get_default()); - } -} - -static Property mpcore_rirq_properties[] =3D { - DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), -}; - -static void mpcore_rirq_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->realize =3D realview_mpcore_realize; - dc->props =3D mpcore_rirq_properties; -} - -static const TypeInfo mpcore_rirq_info =3D { - .name =3D TYPE_REALVIEW_MPCORE_RIRQ, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(mpcore_rirq_state), - .instance_init =3D mpcore_rirq_init, - .class_init =3D mpcore_rirq_class_init, -}; - static Property mpcore_priv_properties[] =3D { DEFINE_PROP_UINT32("num-cpu", ARM11MPCorePriveState, num_cpu, 1), /* The ARM11 MPCORE TRM says the on-chip controller may have @@ -286,7 +166,6 @@ static const TypeInfo mpcore_priv_info =3D { =20 static void arm11mpcore_register_types(void) { - type_register_static(&mpcore_rirq_info); type_register_static(&mpcore_priv_info); } =20 diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c new file mode 100644 index 0000000..c39a2da --- /dev/null +++ b/hw/cpu/realview_mpcore.c @@ -0,0 +1,139 @@ +/* + * RealView ARM11MPCore internal peripheral emulation + * + * Copyright (c) 2006-2007 CodeSourcery. + * Copyright (c) 2013 SUSE LINUX Products GmbH + * Written by Paul Brook and Andreas F=C3=A4rber + * + * This code is licensed under the GPL. + */ + +#include "hw/cpu/arm11mpcore.h" +#include "hw/intc/realview_gic.h" + +#define TYPE_REALVIEW_MPCORE_RIRQ "realview_mpcore" +#define REALVIEW_MPCORE_RIRQ(obj) \ + OBJECT_CHECK(mpcore_rirq_state, (obj), TYPE_REALVIEW_MPCORE_RIRQ) + +/* Dummy PIC to route IRQ lines. The baseboard has 4 independent IRQ + controllers. The output of these, plus some of the raw input lines + are fed into a single SMP-aware interrupt controller on the CPU. */ +typedef struct { + SysBusDevice parent_obj; + + qemu_irq cpuic[32]; + qemu_irq rvic[4][64]; + uint32_t num_cpu; + + ARM11MPCorePriveState priv; + RealViewGICState gic[4]; +} mpcore_rirq_state; + +/* Map baseboard IRQs onto CPU IRQ lines. */ +static const int mpcore_irq_map[32] =3D { + -1, -1, -1, -1, 1, 2, -1, -1, + -1, -1, 6, -1, 4, 5, -1, -1, + -1, 14, 15, 0, 7, 8, -1, -1, + -1, -1, -1, -1, 9, 3, -1, -1, +}; + +static void mpcore_rirq_set_irq(void *opaque, int irq, int level) +{ + mpcore_rirq_state *s =3D (mpcore_rirq_state *)opaque; + int i; + + for (i =3D 0; i < 4; i++) { + qemu_set_irq(s->rvic[i][irq], level); + } + if (irq < 32) { + irq =3D mpcore_irq_map[irq]; + if (irq >=3D 0) { + qemu_set_irq(s->cpuic[irq], level); + } + } +} + +static void realview_mpcore_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); + mpcore_rirq_state *s =3D REALVIEW_MPCORE_RIRQ(dev); + DeviceState *priv =3D DEVICE(&s->priv); + DeviceState *gic; + SysBusDevice *gicbusdev; + Error *err =3D NULL; + int n; + int i; + + qdev_prop_set_uint32(priv, "num-cpu", s->num_cpu); + object_property_set_bool(OBJECT(&s->priv), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + sysbus_pass_irq(sbd, SYS_BUS_DEVICE(&s->priv)); + for (i =3D 0; i < 32; i++) { + s->cpuic[i] =3D qdev_get_gpio_in(priv, i); + } + /* ??? IRQ routing is hardcoded to "normal" mode. */ + for (n =3D 0; n < 4; n++) { + object_property_set_bool(OBJECT(&s->gic[n]), true, "realized", &= err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + gic =3D DEVICE(&s->gic[n]); + gicbusdev =3D SYS_BUS_DEVICE(&s->gic[n]); + sysbus_mmio_map(gicbusdev, 0, 0x10040000 + n * 0x10000); + sysbus_connect_irq(gicbusdev, 0, s->cpuic[10 + n]); + for (i =3D 0; i < 64; i++) { + s->rvic[n][i] =3D qdev_get_gpio_in(gic, i); + } + } + qdev_init_gpio_in(dev, mpcore_rirq_set_irq, 64); +} + +static void mpcore_rirq_init(Object *obj) +{ + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + mpcore_rirq_state *s =3D REALVIEW_MPCORE_RIRQ(obj); + SysBusDevice *privbusdev; + int i; + + object_initialize(&s->priv, sizeof(s->priv), TYPE_ARM11MPCORE_PRIV); + qdev_set_parent_bus(DEVICE(&s->priv), sysbus_get_default()); + privbusdev =3D SYS_BUS_DEVICE(&s->priv); + sysbus_init_mmio(sbd, sysbus_mmio_get_region(privbusdev, 0)); + + for (i =3D 0; i < 4; i++) { + object_initialize(&s->gic[i], sizeof(s->gic[i]), TYPE_REALVIEW_G= IC); + qdev_set_parent_bus(DEVICE(&s->gic[i]), sysbus_get_default()); + } +} + +static Property mpcore_rirq_properties[] =3D { + DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static void mpcore_rirq_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D realview_mpcore_realize; + dc->props =3D mpcore_rirq_properties; +} + +static const TypeInfo mpcore_rirq_info =3D { + .name =3D TYPE_REALVIEW_MPCORE_RIRQ, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(mpcore_rirq_state), + .instance_init =3D mpcore_rirq_init, + .class_init =3D mpcore_rirq_class_init, +}; + +static void realview_mpcore_register_types(void) +{ + type_register_static(&mpcore_rirq_info); +} + +type_init(realview_mpcore_register_types) --=20 1.8.1.4