From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:43000) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VUeIT-0007H0-NU for qemu-devel@nongnu.org; Fri, 11 Oct 2013 11:06:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VUeIO-0005I1-SO for qemu-devel@nongnu.org; Fri, 11 Oct 2013 11:06:33 -0400 Received: from mx1.redhat.com ([209.132.183.28]:45728) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VUeIO-0005Hs-KH for qemu-devel@nongnu.org; Fri, 11 Oct 2013 11:06:28 -0400 From: Kevin Wolf Date: Fri, 11 Oct 2013 17:05:09 +0200 Message-Id: <1381503951-27985-20-git-send-email-kwolf@redhat.com> In-Reply-To: <1381503951-27985-1-git-send-email-kwolf@redhat.com> References: <1381503951-27985-1-git-send-email-kwolf@redhat.com> Subject: [Qemu-devel] [PULL 19/61] ahci: set ahci mode on reset List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: anthony@codemonkey.ws Cc: kwolf@redhat.com, qemu-devel@nongnu.org From: "Michael S. Tsirkin" ATM we set AHCI mode on 1st GHC write. Spec says we should set it on reset. Signed-off-by: Michael S. Tsirkin Signed-off-by: Kevin Wolf --- hw/ide/ahci.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index a71a4ca..a8be62c 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -1198,7 +1198,15 @@ void ahci_reset(AHCIState *s) int i; s->control_regs.irqstatus = 0; - s->control_regs.ghc = 0; + /* AHCI Enable (AE) + * The implementation of this bit is dependent upon the value of the + * CAP.SAM bit. If CAP.SAM is '0', then GHC.AE shall be read-write and + * shall have a reset value of '0'. If CAP.SAM is '1', then AE shall be + * read-only and shall have a reset value of '1'. + * + * We set HOST_CAP_AHCI so we must enable AHCI at reset. + */ + s->control_regs.ghc = HOST_CTL_AHCI_EN; for (i = 0; i < s->ports; i++) { pr = &s->dev[i].port_regs; -- 1.8.1.4