From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:49132) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VWe4H-0004nm-BG for qemu-devel@nongnu.org; Wed, 16 Oct 2013 23:16:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VWe48-00050Q-SY for qemu-devel@nongnu.org; Wed, 16 Oct 2013 23:16:09 -0400 Received: from mail-ob0-x229.google.com ([2607:f8b0:4003:c01::229]:48471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VWe48-00050M-NO for qemu-devel@nongnu.org; Wed, 16 Oct 2013 23:16:00 -0400 Received: by mail-ob0-f169.google.com with SMTP id wp4so1409536obc.14 for ; Wed, 16 Oct 2013 20:16:00 -0700 (PDT) From: Liu Ping Fan Date: Thu, 17 Oct 2013 11:16:03 +0800 Message-Id: <1381979765-23092-3-git-send-email-pingfank@linux.vnet.ibm.com> In-Reply-To: <1381979765-23092-1-git-send-email-pingfank@linux.vnet.ibm.com> References: <1381979765-23092-1-git-send-email-pingfank@linux.vnet.ibm.com> Subject: [Qemu-devel] [PATCH v7 2/4] hpet: enable to entitle more irq pins for hpet List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Anthony Liguori , "Michael S. Tsirkin" On q35, IRQ2/8 can be reserved for hpet timer 0/1. And pin 16~23 of ioapic can be dynamically assigned to hpet as guest chooses. So we introduce intcap property to do that. (currently, its value is IRQ2. Later, it should be set by board.) Signed-off-by: Liu Ping Fan --- hw/timer/hpet.c | 12 ++++++++++-- include/hw/i386/pc.h | 2 ++ 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 8429eb3..48a13bf 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -42,6 +42,9 @@ #define HPET_MSI_SUPPORT 0 +/* Will fix: intcap is set by board, and should be 0 if nobody sets. */ +#define HPET_TN_INT_CAP_DEFAULT 0x4ULL + #define TYPE_HPET "hpet" #define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET) @@ -73,6 +76,7 @@ typedef struct HPETState { uint8_t rtc_irq_level; qemu_irq pit_enabled; uint8_t num_timers; + uint32_t intcap; HPETTimer timer[HPET_MAX_TIMERS]; /* Memory-mapped, software visible registers */ @@ -663,8 +667,8 @@ static void hpet_reset(DeviceState *d) if (s->flags & (1 << HPET_MSI_SUPPORT)) { timer->config |= HPET_TN_FSB_CAP; } - /* advertise availability of ioapic inti2 */ - timer->config |= 0x00000004ULL << 32; + /* advertise availability of ioapic int */ + timer->config |= (uint64_t)s->intcap << 32; timer->period = 0ULL; timer->wrap_flag = 0; } @@ -713,6 +717,9 @@ static void hpet_realize(DeviceState *dev, Error **errp) int i; HPETTimer *timer; + if (!s->intcap) { + error_printf("Hpet's intcap not initialized.\n"); + } if (hpet_cfg.count == UINT8_MAX) { /* first instance */ hpet_cfg.count = 0; @@ -753,6 +760,7 @@ static void hpet_realize(DeviceState *dev, Error **errp) static Property hpet_device_properties[] = { DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS), DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false), + DEFINE_PROP_UINT32(HPET_INTCAP, HPETState, intcap, HPET_TN_INT_CAP_DEFAULT), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 9b2ddc4..1361a27 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -10,6 +10,8 @@ #include "qemu/range.h" +#define HPET_INTCAP "hpet-intcap" + /* PC-style peripherals (also used by other machines). */ typedef struct PcPciInfo { -- 1.8.1.4