From: Sebastian Macke <sebastian@macke.de>
To: qemu-devel@nongnu.org, proljc@gmail.com
Cc: sebastian@macke.de, openrisc@lists.openrisc.net,
openrisc@lists.opencores.org
Subject: [Qemu-devel] [PATCH_v2 7/9] target-openrisc: Separate branch flag from Supervision register
Date: Tue, 22 Oct 2013 02:12:43 +0200 [thread overview]
Message-ID: <1382400765-26377-8-git-send-email-sebastian@macke.de> (raw)
In-Reply-To: <1382400765-26377-1-git-send-email-sebastian@macke.de>
The branch flag is very often used. To increase the speed
the flag is separated. This patch removes several
ands and ors and branches from the generated code.
The additional flag btaken is no longer necessary.
Signed-off-by: Sebastian Macke <sebastian@macke.de>
---
target-openrisc/cpu.c | 1 +
target-openrisc/cpu.h | 13 +++--
target-openrisc/gdbstub.c | 4 +-
target-openrisc/interrupt.c | 2 +-
target-openrisc/interrupt_helper.c | 2 +-
target-openrisc/machine.c | 1 +
target-openrisc/sys_helper.c | 6 +--
target-openrisc/translate.c | 99 +++++++++++++++-----------------------
8 files changed, 57 insertions(+), 71 deletions(-)
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c
index 8137943..09ba728 100644
--- a/target-openrisc/cpu.c
+++ b/target-openrisc/cpu.c
@@ -42,6 +42,7 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.pc = 0x100;
cpu->env.sr = SR_FO | SR_SM;
+ cpu->env.srf = 0;
cpu->env.exception_index = -1;
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP;
diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h
index 0f9efdf..ab87cd2 100644
--- a/target-openrisc/cpu.h
+++ b/target-openrisc/cpu.h
@@ -272,6 +272,14 @@ typedef struct CPUOpenRISCTLBContext {
} CPUOpenRISCTLBContext;
#endif
+/* Helper for the supervision register */
+#define ENV_GET_SR(env) (((env)->sr&~SR_F) | ((env)->srf ? SR_F : 0))
+
+#define ENV_SET_SR(env, srtemp) do {\
+ (env)->sr = ((srtemp) & ~SR_F) | SR_FO;\
+ (env)->srf = (srtemp) & SR_F;\
+ } while (0)
+
typedef struct CPUOpenRISCState {
target_ulong gpr[32]; /* General registers */
target_ulong pc; /* Program counter */
@@ -288,7 +296,8 @@ typedef struct CPUOpenRISCState {
target_ulong epcr; /* Exception PC register */
target_ulong eear; /* Exception EA register */
- uint32_t sr; /* Supervisor register */
+ uint32_t sr; /* Supervision register */
+ uint32_t srf; /* separated branch flag of Supervision register*/
uint32_t vr; /* Version register */
uint32_t upr; /* Unit presence register */
uint32_t cpucfgr; /* CPU configure register */
@@ -300,8 +309,6 @@ typedef struct CPUOpenRISCState {
uint32_t flags; /* cpu_flags, we only use it for exception
in solt so far. */
- uint32_t btaken; /* the SR_F bit */
-
CPU_COMMON
#ifndef CONFIG_USER_ONLY
diff --git a/target-openrisc/gdbstub.c b/target-openrisc/gdbstub.c
index 18bcc46..81acf2d 100644
--- a/target-openrisc/gdbstub.c
+++ b/target-openrisc/gdbstub.c
@@ -37,7 +37,7 @@ int openrisc_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
return gdb_get_reg32(mem_buf, env->npc);
case 34: /* SR */
- return gdb_get_reg32(mem_buf, env->sr);
+ return gdb_get_reg32(mem_buf, ENV_GET_SR(env));
default:
break;
@@ -72,7 +72,7 @@ int openrisc_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
break;
case 34: /* SR */
- env->sr = tmp;
+ ENV_SET_SR(env, tmp);
break;
default:
diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c
index 2153e7e..d1d6ae2 100644
--- a/target-openrisc/interrupt.c
+++ b/target-openrisc/interrupt.c
@@ -45,7 +45,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
we need flush TLB when we enter&exit EXCP. */
tlb_flush(env, 1);
- env->esr = env->sr;
+ env->esr = ENV_GET_SR(env);
env->sr &= ~SR_DME;
env->sr &= ~SR_IME;
env->sr |= SR_SM;
diff --git a/target-openrisc/interrupt_helper.c b/target-openrisc/interrupt_helper.c
index 844648f..8a07b09 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -31,7 +31,7 @@ void HELPER(rfe)(CPUOpenRISCState *env)
#endif
cpu->env.pc = cpu->env.epcr;
cpu->env.npc = cpu->env.epcr;
- cpu->env.sr = cpu->env.esr;
+ ENV_SET_SR(&(cpu->env), cpu->env.esr);
#ifndef CONFIG_USER_ONLY
if (cpu->env.sr & SR_DME) {
diff --git a/target-openrisc/machine.c b/target-openrisc/machine.c
index 6f864fe..2bdd40f 100644
--- a/target-openrisc/machine.c
+++ b/target-openrisc/machine.c
@@ -28,6 +28,7 @@ static const VMStateDescription vmstate_env = {
.fields = (VMStateField[]) {
VMSTATE_UINT32_ARRAY(gpr, CPUOpenRISCState, 32),
VMSTATE_UINT32(sr, CPUOpenRISCState),
+ VMSTATE_UINT32(srf, CPUOpenRISCState),
VMSTATE_UINT32(epcr, CPUOpenRISCState),
VMSTATE_UINT32(eear, CPUOpenRISCState),
VMSTATE_UINT32(esr, CPUOpenRISCState),
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index be06c45..1d0651a 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -47,8 +47,8 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
(rb & (SR_IME | SR_DME | SR_SM))) {
tlb_flush(env, 1);
}
- env->sr = rb;
- env->sr |= SR_FO; /* FO is const equal to 1 */
+ ENV_SET_SR(env, rb);
+
if (env->sr & SR_DME) {
env->tlb->cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_data;
@@ -198,7 +198,7 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
return env->npc;
case TO_SPR(0, 17): /* SR */
- return env->sr;
+ return ENV_GET_SR(env);
case TO_SPR(0, 18): /* PPC */
return env->ppc;
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index 91c60eb..1ae807f 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -51,12 +51,12 @@ typedef struct DisasContext {
static TCGv_ptr cpu_env;
static TCGv cpu_sr;
+static TCGv cpu_srf;
static TCGv cpu_R[32];
static TCGv cpu_pc;
static TCGv jmp_pc; /* l.jr/l.jalr temp pc */
static TCGv cpu_npc;
static TCGv cpu_ppc;
-static TCGv_i32 env_btaken; /* bf/bnf , F flag taken */
static TCGv_i32 fpcsr;
static TCGv machi, maclo;
static TCGv fpmaddhi, fpmaddlo;
@@ -76,6 +76,8 @@ void openrisc_translate_init(void)
cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
cpu_sr = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, sr), "sr");
+ cpu_srf = tcg_global_mem_new(TCG_AREG0,
+ offsetof(CPUOpenRISCState, srf), "srf");
env_flags = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUOpenRISCState, flags),
"flags");
@@ -87,9 +89,6 @@ void openrisc_translate_init(void)
offsetof(CPUOpenRISCState, ppc), "ppc");
jmp_pc = tcg_global_mem_new(TCG_AREG0,
offsetof(CPUOpenRISCState, jmp_pc), "jmp_pc");
- env_btaken = tcg_global_mem_new_i32(TCG_AREG0,
- offsetof(CPUOpenRISCState, btaken),
- "btaken");
fpcsr = tcg_global_mem_new_i32(TCG_AREG0,
offsetof(CPUOpenRISCState, fpcsr),
"fpcsr");
@@ -112,17 +111,6 @@ void openrisc_translate_init(void)
}
}
-/* Writeback SR_F transaltion-space to execution-space. */
-static inline void wb_SR_F(void)
-{
- int label;
-
- label = gen_new_label();
- tcg_gen_andi_tl(cpu_sr, cpu_sr, ~SR_F);
- tcg_gen_brcondi_tl(TCG_COND_EQ, env_btaken, 0, label);
- tcg_gen_ori_tl(cpu_sr, cpu_sr, SR_F);
- gen_set_label(label);
-}
static inline int zero_extend(unsigned int val, int width)
{
@@ -224,14 +212,11 @@ static void gen_jump(DisasContext *dc, uint32_t imm, uint32_t reg, uint32_t op0)
case 0x04: /* l.bf */
{
int lab = gen_new_label();
- TCGv sr_f = tcg_temp_new();
tcg_gen_movi_tl(jmp_pc, dc->pc+8);
- tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
- tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_EQ : TCG_COND_NE,
- sr_f, SR_F, lab);
+ tcg_gen_brcondi_i32(op0 == 0x03 ? TCG_COND_NE : TCG_COND_EQ,
+ cpu_srf, 0, lab);
tcg_gen_movi_tl(jmp_pc, tmp_pc);
gen_set_label(lab);
- tcg_temp_free(sr_f);
}
break;
case 0x11: /* l.jr */
@@ -567,14 +552,11 @@ static void dec_calc(DisasContext *dc, uint32_t insn)
{
int lab = gen_new_label();
TCGv res = tcg_temp_local_new();
- TCGv sr_f = tcg_temp_new();
- tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
tcg_gen_mov_tl(res, cpu_R[rb]);
- tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
+ tcg_gen_brcondi_tl(TCG_COND_NE, cpu_srf, SR_F, lab);
tcg_gen_mov_tl(res, cpu_R[ra]);
gen_set_label(lab);
tcg_gen_mov_tl(cpu_R[rd], res);
- tcg_temp_free(sr_f);
tcg_temp_free(res);
}
break;
@@ -1213,7 +1195,6 @@ static void dec_comp(DisasContext *dc, uint32_t insn)
ra = extract32(insn, 16, 5);
rb = extract32(insn, 11, 5);
- tcg_gen_movi_i32(env_btaken, 0x0);
/* unsigned integers */
tcg_gen_ext32u_tl(cpu_R[ra], cpu_R[ra]);
tcg_gen_ext32u_tl(cpu_R[rb], cpu_R[rb]);
@@ -1221,59 +1202,58 @@ static void dec_comp(DisasContext *dc, uint32_t insn)
switch (op0) {
case 0x0: /* l.sfeq */
LOG_DIS("l.sfeq r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_EQ, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
case 0x1: /* l.sfne */
LOG_DIS("l.sfne r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_NE, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_NE, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
case 0x2: /* l.sfgtu */
LOG_DIS("l.sfgtu r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_GTU, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
case 0x3: /* l.sfgeu */
LOG_DIS("l.sfgeu r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_GEU, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
case 0x4: /* l.sfltu */
LOG_DIS("l.sfltu r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_LTU, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
case 0x5: /* l.sfleu */
LOG_DIS("l.sfleu r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_LEU, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
case 0xa: /* l.sfgts */
LOG_DIS("l.sfgts r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_GT, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_GT, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
case 0xb: /* l.sfges */
LOG_DIS("l.sfges r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_GE, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_GE, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
case 0xc: /* l.sflts */
LOG_DIS("l.sflts r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_LT, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_LT, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
case 0xd: /* l.sfles */
LOG_DIS("l.sfles r%d, r%d\n", ra, rb);
- tcg_gen_setcond_tl(TCG_COND_LE, env_btaken, cpu_R[ra], cpu_R[rb]);
+ tcg_gen_setcond_tl(TCG_COND_LE, cpu_srf, cpu_R[ra], cpu_R[rb]);
break;
default:
gen_illegal_exception(dc);
break;
}
- wb_SR_F();
}
static void dec_compi(DisasContext *dc, uint32_t insn)
@@ -1285,65 +1265,63 @@ static void dec_compi(DisasContext *dc, uint32_t insn)
ra = extract32(insn, 16, 5);
I16 = extract32(insn, 0, 16);
- tcg_gen_movi_i32(env_btaken, 0x0);
I16 = sign_extend(I16, 16);
switch (op0) {
case 0x0: /* l.sfeqi */
LOG_DIS("l.sfeqi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_EQ, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_srf, cpu_R[ra], I16);
break;
case 0x1: /* l.sfnei */
LOG_DIS("l.sfnei r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_NE, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_NE, cpu_srf, cpu_R[ra], I16);
break;
case 0x2: /* l.sfgtui */
LOG_DIS("l.sfgtui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GTU, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_srf, cpu_R[ra], I16);
break;
case 0x3: /* l.sfgeui */
LOG_DIS("l.sfgeui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GEU, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_srf, cpu_R[ra], I16);
break;
case 0x4: /* l.sfltui */
LOG_DIS("l.sfltui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LTU, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_srf, cpu_R[ra], I16);
break;
case 0x5: /* l.sfleui */
LOG_DIS("l.sfleui r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LEU, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_srf, cpu_R[ra], I16);
break;
case 0xa: /* l.sfgtsi */
LOG_DIS("l.sfgtsi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GT, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_GT, cpu_srf, cpu_R[ra], I16);
break;
case 0xb: /* l.sfgesi */
LOG_DIS("l.sfgesi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_GE, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_GE, cpu_srf, cpu_R[ra], I16);
break;
case 0xc: /* l.sfltsi */
LOG_DIS("l.sfltsi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LT, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_LT, cpu_srf, cpu_R[ra], I16);
break;
case 0xd: /* l.sflesi */
LOG_DIS("l.sflesi r%d, %d\n", ra, I16);
- tcg_gen_setcondi_tl(TCG_COND_LE, env_btaken, cpu_R[ra], I16);
+ tcg_gen_setcondi_tl(TCG_COND_LE, cpu_srf, cpu_R[ra], I16);
break;
default:
gen_illegal_exception(dc);
break;
}
- wb_SR_F();
}
static void dec_sys(DisasContext *dc, uint32_t insn)
@@ -1479,32 +1457,32 @@ static void dec_float(DisasContext *dc, uint32_t insn)
case 0x08: /* lf.sfeq.s */
LOG_DIS("lf.sfeq.s r%d, r%d\n", ra, rb);
- gen_helper_float_eq_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_eq_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x09: /* lf.sfne.s */
LOG_DIS("lf.sfne.s r%d, r%d\n", ra, rb);
- gen_helper_float_ne_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_ne_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x0a: /* lf.sfgt.s */
LOG_DIS("lf.sfgt.s r%d, r%d\n", ra, rb);
- gen_helper_float_gt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_gt_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x0b: /* lf.sfge.s */
LOG_DIS("lf.sfge.s r%d, r%d\n", ra, rb);
- gen_helper_float_ge_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_ge_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x0c: /* lf.sflt.s */
LOG_DIS("lf.sflt.s r%d, r%d\n", ra, rb);
- gen_helper_float_lt_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_lt_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x0d: /* lf.sfle.s */
LOG_DIS("lf.sfle.s r%d, r%d\n", ra, rb);
- gen_helper_float_le_s(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_le_s(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
/* not used yet, open it when we need or64. */
@@ -1565,37 +1543,37 @@ static void dec_float(DisasContext *dc, uint32_t insn)
case 0x18: lf.sfeq.d
LOG_DIS("lf.sfeq.d r%d, r%d\n", ra, rb);
check_of64s(dc);
- gen_helper_float_eq_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_eq_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x1a: lf.sfgt.d
LOG_DIS("lf.sfgt.d r%d, r%d\n", ra, rb);
check_of64s(dc);
- gen_helper_float_gt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_gt_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x1b: lf.sfge.d
LOG_DIS("lf.sfge.d r%d, r%d\n", ra, rb);
check_of64s(dc);
- gen_helper_float_ge_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_ge_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x19: lf.sfne.d
LOG_DIS("lf.sfne.d r%d, r%d\n", ra, rb);
check_of64s(dc);
- gen_helper_float_ne_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_ne_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x1c: lf.sflt.d
LOG_DIS("lf.sflt.d r%d, r%d\n", ra, rb);
check_of64s(dc);
- gen_helper_float_lt_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_lt_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
case 0x1d: lf.sfle.d
LOG_DIS("lf.sfle.d r%d, r%d\n", ra, rb);
check_of64s(dc);
- gen_helper_float_le_d(env_btaken, cpu_env, cpu_R[ra], cpu_R[rb]);
+ gen_helper_float_le_d(cpu_srf, cpu_env, cpu_R[ra], cpu_R[rb]);
break;
#endif*/
@@ -1603,7 +1581,6 @@ static void dec_float(DisasContext *dc, uint32_t insn)
gen_illegal_exception(dc);
break;
}
- wb_SR_F();
}
static void disas_openrisc_insn(DisasContext *dc, OpenRISCCPU *cpu)
--
1.8.4.1
next prev parent reply other threads:[~2013-10-22 0:13 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-10-22 0:12 [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements Sebastian Macke
2013-10-22 0:12 ` [Qemu-devel] [PATCH_v2 1/9] target-openrisc: Speed up move instruction Sebastian Macke
2013-10-22 0:12 ` [Qemu-devel] [PATCH_v2 2/9] target-openrisc: Remove unnecessary code generated by jump instructions Sebastian Macke
2013-10-22 0:12 ` [Qemu-devel] [PATCH_v2 3/9] target-openrisc: Remove executable flag for every page Sebastian Macke
2013-10-22 0:12 ` [Qemu-devel] [PATCH_v2 4/9] target-openrisc: Correct wrong epcr register in interrupt handler Sebastian Macke
2013-10-22 0:12 ` [Qemu-devel] [PATCH_v2 5/9] openrisc-timer: Reduce overhead, Separate clock update functions Sebastian Macke
2013-10-22 0:12 ` [Qemu-devel] [PATCH_v2 6/9] target-openrisc: Correct memory bounds checking for the tlb buffers Sebastian Macke
2013-10-22 0:12 ` Sebastian Macke [this message]
2013-10-22 0:12 ` [Qemu-devel] [PATCH_v2 8/9] target-openrisc: Complete remove of npc and ppc variables Sebastian Macke
2013-10-22 0:12 ` [Qemu-devel] [PATCH_v2 9/9] target-openrisc: Correct carry flag check of l.addc and l.addic test cases Sebastian Macke
2013-10-22 8:35 ` [Qemu-devel] [PATCH_v2 9/9] target-openrisc: Correct carry flagcheck of l.addc and l.addic test casess Alex Bennée
2013-10-22 15:45 ` Sebastian Macke
2013-10-22 16:01 ` Max Filippov
2013-10-22 16:12 ` Alex Bennée
2013-10-22 16:15 ` Sebastian Macke
2013-10-23 6:52 ` Max Filippov
2013-10-23 3:47 ` [Qemu-devel] [PATCH_v2 0/9] target-openrisc: Corrections and speed improvements Jia Liu
2013-10-24 23:23 ` Sebastian Macke
2013-10-26 0:21 ` Jia Liu
2013-10-28 1:56 ` Sebastian Macke
2013-10-29 7:32 ` Jia Liu
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