From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34301) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZSCj-0002bO-NA for qemu-devel@nongnu.org; Thu, 24 Oct 2013 17:12:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VZSCb-0006Re-9j for qemu-devel@nongnu.org; Thu, 24 Oct 2013 17:12:29 -0400 Received: from mail-lb0-x229.google.com ([2a00:1450:4010:c04::229]:38685) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZSCb-0006RP-1m for qemu-devel@nongnu.org; Thu, 24 Oct 2013 17:12:21 -0400 Received: by mail-lb0-f169.google.com with SMTP id o14so73071lbi.14 for ; Thu, 24 Oct 2013 14:12:20 -0700 (PDT) Received: from localhost (h59ec325f.selukar.dyn.perspektivbredband.net. [89.236.50.95]) by mx.google.com with ESMTPSA id os9sm159441lbb.17.2013.10.24.14.12.18 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 24 Oct 2013 14:12:19 -0700 (PDT) From: edgar.iglesias@gmail.com Date: Thu, 24 Oct 2013 23:08:52 +0200 Message-Id: <1382648937-14769-6-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1382648937-14769-1-git-send-email-edgar.iglesias@gmail.com> References: <1382648937-14769-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH 05/10] microblaze: Improve src List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" Microblaze carry is mirrored in MSR[31], pick it directly from there. Also, no need to mask cpu_R[dc->ra] when calling write_carry. 15% improvement in linux-user src loops. Signed-off-by: Edgar E. Iglesias --- target-microblaze/translate.c | 15 ++++----------- 1 file changed, 4 insertions(+), 11 deletions(-) diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 93aafac..232015a 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -750,7 +750,7 @@ static void dec_barrel(DisasContext *dc) static void dec_bit(DisasContext *dc) { - TCGv t0, t1; + TCGv t0; unsigned int op; int mem_index = cpu_mmu_index(dc->env); @@ -761,19 +761,12 @@ static void dec_bit(DisasContext *dc) t0 = tcg_temp_new(); LOG_DIS("src r%d r%d\n", dc->rd, dc->ra); - tcg_gen_andi_tl(t0, cpu_R[dc->ra], 1); + tcg_gen_andi_tl(t0, cpu_SR[SR_MSR], MSR_CC); + write_carry(dc, cpu_R[dc->ra]); if (dc->rd) { - t1 = tcg_temp_new(); - read_carry(dc, t1); - tcg_gen_shli_tl(t1, t1, 31); - tcg_gen_shri_tl(cpu_R[dc->rd], cpu_R[dc->ra], 1); - tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t1); - tcg_temp_free(t1); + tcg_gen_or_tl(cpu_R[dc->rd], cpu_R[dc->rd], t0); } - - /* Update carry. */ - write_carry(dc, t0); tcg_temp_free(t0); break; -- 1.7.10.4