From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34411) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZSCn-0002hF-Qz for qemu-devel@nongnu.org; Thu, 24 Oct 2013 17:12:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VZSCf-0006TF-F2 for qemu-devel@nongnu.org; Thu, 24 Oct 2013 17:12:33 -0400 Received: from mail-lb0-x234.google.com ([2a00:1450:4010:c04::234]:56431) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZSCf-0006Sw-5c for qemu-devel@nongnu.org; Thu, 24 Oct 2013 17:12:25 -0400 Received: by mail-lb0-f180.google.com with SMTP id y6so68271lbh.25 for ; Thu, 24 Oct 2013 14:12:24 -0700 (PDT) Received: from localhost (h59ec325f.selukar.dyn.perspektivbredband.net. [89.236.50.95]) by mx.google.com with ESMTPSA id ao4sm3254891lac.1.2013.10.24.14.12.21 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 24 Oct 2013 14:12:22 -0700 (PDT) From: edgar.iglesias@gmail.com Date: Thu, 24 Oct 2013 23:08:53 +0200 Message-Id: <1382648937-14769-7-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1382648937-14769-1-git-send-email-edgar.iglesias@gmail.com> References: <1382648937-14769-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH 06/10] microblaze: Move the saving of the reservation addr into gen_load List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" No functional change. Signed-off-by: Edgar E. Iglesias --- target-microblaze/translate.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 232015a..021a504 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -863,7 +863,7 @@ static void dec_imm(DisasContext *dc) } static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr, - unsigned int size) + unsigned int size, bool exclusive) { int mem_index = cpu_mmu_index(dc->env); @@ -875,6 +875,10 @@ static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr, tcg_gen_qemu_ld32u(dst, addr, mem_index); } else cpu_abort(dc->env, "Incorrect load size %d\n", size); + + if (exclusive) { + tcg_gen_st_tl(addr, cpu_env, offsetof(CPUMBState, res_addr)); + } } static inline TCGv *compute_ldst_addr(DisasContext *dc, TCGv *t) @@ -1046,7 +1050,7 @@ static void dec_load(DisasContext *dc) * into v. If the load succeeds, we verify alignment of the * address and if that succeeds we write into the destination reg. */ - gen_load(dc, v, *addr, size); + gen_load(dc, v, *addr, size, ex); tcg_gen_movi_tl(cpu_SR[SR_PC], dc->pc); gen_helper_memalign(cpu_env, *addr, tcg_const_tl(dc->rd), @@ -1061,20 +1065,19 @@ static void dec_load(DisasContext *dc) tcg_temp_free(v); } else { if (dc->rd) { - gen_load(dc, cpu_R[dc->rd], *addr, size); + gen_load(dc, cpu_R[dc->rd], *addr, size, ex); if (rev) { dec_byteswap(dc, cpu_R[dc->rd], cpu_R[dc->rd], size); } } else { /* We are loading into r0, no need to reverse. */ - gen_load(dc, env_imm, *addr, size); + gen_load(dc, env_imm, *addr, size, ex); } } if (ex) { /* lwx */ /* no support for for AXI exclusive so always clear C */ write_carryi(dc, 0); - tcg_gen_st_tl(*addr, cpu_env, offsetof(CPUMBState, res_addr)); } if (addr == &t) -- 1.7.10.4