From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:34601) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZSCz-0002zj-6Q for qemu-devel@nongnu.org; Thu, 24 Oct 2013 17:12:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1VZSCq-0006bK-F9 for qemu-devel@nongnu.org; Thu, 24 Oct 2013 17:12:45 -0400 Received: from mail-lb0-x22a.google.com ([2a00:1450:4010:c04::22a]:52383) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1VZSCq-0006Zt-58 for qemu-devel@nongnu.org; Thu, 24 Oct 2013 17:12:36 -0400 Received: by mail-lb0-f170.google.com with SMTP id u14so76211lbd.1 for ; Thu, 24 Oct 2013 14:12:35 -0700 (PDT) Received: from localhost (h59ec325f.selukar.dyn.perspektivbredband.net. [89.236.50.95]) by mx.google.com with ESMTPSA id vo1sm198856lbb.1.2013.10.24.14.12.29 for (version=TLSv1.2 cipher=RC4-SHA bits=128/128); Thu, 24 Oct 2013 14:12:30 -0700 (PDT) From: edgar.iglesias@gmail.com Date: Thu, 24 Oct 2013 23:08:55 +0200 Message-Id: <1382648937-14769-9-git-send-email-edgar.iglesias@gmail.com> In-Reply-To: <1382648937-14769-1-git-send-email-edgar.iglesias@gmail.com> References: <1382648937-14769-1-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] [PATCH 08/10] microblaze: At swx, check that the reserved word is unmodified List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: "Edgar E. Iglesias" This improves the reservation check for system emulation, making it possible to catch stores that modify reserved word. Signed-off-by: Edgar E. Iglesias --- target-microblaze/cpu.h | 1 + target-microblaze/translate.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+) diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 7508cf5..e1415f0 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -246,6 +246,7 @@ struct CPUMBState { /* lwx/swx reserved address */ #define RES_ADDR_NONE 0xffffffff /* Use 0xffffffff to indicate no reservation */ uint32_t res_addr; + uint32_t res_val; /* Internal flags. */ #define IMM_FLAG 4 diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index 57627fc..9edcb67 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -50,6 +50,7 @@ static TCGv env_btaken; static TCGv env_btarget; static TCGv env_iflags; static TCGv env_res_addr; +static TCGv env_res_val; #include "exec/gen-icount.h" @@ -879,6 +880,7 @@ static inline void gen_load(DisasContext *dc, TCGv dst, TCGv addr, if (exclusive) { tcg_gen_mov_tl(env_res_addr, addr); + tcg_gen_mov_tl(env_res_val, dst); } } @@ -1128,6 +1130,7 @@ static void dec_store(DisasContext *dc) swx_addr = tcg_temp_local_new(); if (ex) { /* swx */ + TCGv tval; /* Force addr into the swx_addr. */ tcg_gen_mov_tl(swx_addr, *addr); @@ -1138,7 +1141,17 @@ static void dec_store(DisasContext *dc) write_carryi(dc, 1); swx_skip = gen_new_label(); tcg_gen_brcond_tl(TCG_COND_NE, env_res_addr, swx_addr, swx_skip); + + /* Compare the value loaded at lwx with current contents of + the reserved location. + FIXME: This only works for system emulation where we can expect + this compare and the following write to be atomic. For user + emulation we need to add atomicity between threads. */ + tval = tcg_temp_new(); + gen_load(dc, tval, swx_addr, 4, false); + tcg_gen_brcond_tl(TCG_COND_NE, env_res_val, tval, swx_skip); write_carryi(dc, 0); + tcg_temp_free(tval); } if (rev && size != 4) { @@ -2009,6 +2022,9 @@ void mb_tcg_init(void) env_res_addr = tcg_global_mem_new(TCG_AREG0, offsetof(CPUMBState, res_addr), "res_addr"); + env_res_val = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUMBState, res_val), + "res_val"); for (i = 0; i < ARRAY_SIZE(cpu_R); i++) { cpu_R[i] = tcg_global_mem_new(TCG_AREG0, offsetof(CPUMBState, regs[i]), -- 1.7.10.4